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ef9e41df68
A missing shift made updates to the low order bits of timecmp erroneously copy the old low order bits into the high order bits of the 64-bit timecmp register. Add the missing shift and rename timecmp local variables to timecmp_hi and timecmp_lo. This bug didn't show up as the low order bits are usually written first followed by the high order bits meaning the high order bits contained an invalid value between the timecmp_lo and timecmp_hi update. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Co-Authored-by: Johannes Haring <johannes.haring@gmx.net> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
252 lines
8.6 KiB
C
252 lines
8.6 KiB
C
/*
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* SiFive CLINT (Core Local Interruptor)
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This provides real-time clock, timer and interprocessor interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/sifive_clint.h"
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#include "qemu/timer.h"
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static uint64_t cpu_riscv_read_rtc(void)
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{
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
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}
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/*
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* Called when timecmp is written to update the QEMU timer or immediately
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* trigger timer interrupt if mtimecmp <= current timer value.
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*/
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static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
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{
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uint64_t next;
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uint64_t diff;
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uint64_t rtc_r = cpu_riscv_read_rtc();
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cpu->env.timecmp = value;
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if (cpu->env.timecmp <= rtc_r) {
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/* if we're setting an MTIMECMP value in the "past",
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immediately raise the timer interrupt */
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riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
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return;
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}
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/* otherwise, set up the future timer interrupt */
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riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
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diff = cpu->env.timecmp - rtc_r;
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/* back to ns (note args switched in muldiv64) */
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
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timer_mod(cpu->env.timer, next);
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}
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/*
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* Callback used when the timer set using timer_mod expires.
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* Should raise the timer interrupt line
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*/
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static void sifive_clint_timer_cb(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
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}
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/* CPU wants to read rtc or timecmp register */
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static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
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{
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SiFiveCLINTState *clint = opaque;
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if (addr >= clint->sip_base &&
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addr < clint->sip_base + (clint->num_harts << 2)) {
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size_t hartid = (addr - clint->sip_base) >> 2;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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error_report("clint: invalid timecmp hartid: %zu", hartid);
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} else if ((addr & 0x3) == 0) {
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return (env->mip & MIP_MSIP) > 0;
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} else {
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error_report("clint: invalid read: %08x", (uint32_t)addr);
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return 0;
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}
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} else if (addr >= clint->timecmp_base &&
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addr < clint->timecmp_base + (clint->num_harts << 3)) {
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size_t hartid = (addr - clint->timecmp_base) >> 3;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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error_report("clint: invalid timecmp hartid: %zu", hartid);
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} else if ((addr & 0x7) == 0) {
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/* timecmp_lo */
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uint64_t timecmp = env->timecmp;
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return timecmp & 0xFFFFFFFF;
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} else if ((addr & 0x7) == 4) {
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/* timecmp_hi */
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uint64_t timecmp = env->timecmp;
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return (timecmp >> 32) & 0xFFFFFFFF;
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} else {
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error_report("clint: invalid read: %08x", (uint32_t)addr);
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return 0;
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}
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} else if (addr == clint->time_base) {
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/* time_lo */
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return cpu_riscv_read_rtc() & 0xFFFFFFFF;
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} else if (addr == clint->time_base + 4) {
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/* time_hi */
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return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
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}
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error_report("clint: invalid read: %08x", (uint32_t)addr);
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return 0;
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}
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/* CPU wrote to rtc or timecmp register */
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static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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SiFiveCLINTState *clint = opaque;
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if (addr >= clint->sip_base &&
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addr < clint->sip_base + (clint->num_harts << 2)) {
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size_t hartid = (addr - clint->sip_base) >> 2;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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error_report("clint: invalid timecmp hartid: %zu", hartid);
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} else if ((addr & 0x3) == 0) {
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riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
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} else {
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error_report("clint: invalid sip write: %08x", (uint32_t)addr);
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}
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return;
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} else if (addr >= clint->timecmp_base &&
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addr < clint->timecmp_base + (clint->num_harts << 3)) {
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size_t hartid = (addr - clint->timecmp_base) >> 3;
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CPUState *cpu = qemu_get_cpu(hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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error_report("clint: invalid timecmp hartid: %zu", hartid);
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} else if ((addr & 0x7) == 0) {
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/* timecmp_lo */
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uint64_t timecmp_hi = env->timecmp >> 32;
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sifive_clint_write_timecmp(RISCV_CPU(cpu),
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timecmp_hi << 32 | (value & 0xFFFFFFFF));
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return;
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} else if ((addr & 0x7) == 4) {
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/* timecmp_hi */
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uint64_t timecmp_lo = env->timecmp;
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sifive_clint_write_timecmp(RISCV_CPU(cpu),
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value << 32 | (timecmp_lo & 0xFFFFFFFF));
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} else {
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error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
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}
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return;
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} else if (addr == clint->time_base) {
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/* time_lo */
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error_report("clint: time_lo write not implemented");
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return;
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} else if (addr == clint->time_base + 4) {
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/* time_hi */
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error_report("clint: time_hi write not implemented");
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return;
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}
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error_report("clint: invalid write: %08x", (uint32_t)addr);
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}
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static const MemoryRegionOps sifive_clint_ops = {
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.read = sifive_clint_read,
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.write = sifive_clint_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static Property sifive_clint_properties[] = {
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DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
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DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
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DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
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DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
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DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void sifive_clint_realize(DeviceState *dev, Error **errp)
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{
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SiFiveCLINTState *s = SIFIVE_CLINT(dev);
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memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
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TYPE_SIFIVE_CLINT, s->aperture_size);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
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}
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static void sifive_clint_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = sifive_clint_realize;
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dc->props = sifive_clint_properties;
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}
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static const TypeInfo sifive_clint_info = {
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.name = TYPE_SIFIVE_CLINT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFiveCLINTState),
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.class_init = sifive_clint_class_init,
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};
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static void sifive_clint_register_types(void)
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{
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type_register_static(&sifive_clint_info);
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}
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type_init(sifive_clint_register_types)
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/*
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* Create CLINT device.
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*/
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DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
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uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base)
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{
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int i;
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for (i = 0; i < num_harts; i++) {
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CPUState *cpu = qemu_get_cpu(i);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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if (!env) {
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continue;
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}
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env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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&sifive_clint_timer_cb, cpu);
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env->timecmp = 0;
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}
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DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
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qdev_prop_set_uint32(dev, "num-harts", num_harts);
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qdev_prop_set_uint32(dev, "sip-base", sip_base);
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qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
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qdev_prop_set_uint32(dev, "time-base", time_base);
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qdev_prop_set_uint32(dev, "aperture-size", size);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
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return dev;
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}
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