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db873cc5d1
This is the same transformation as in the previous commit, except sysbus_init_child_obj() and realize are too separated for the commit's Coccinelle script to handle, typically because sysbus_init_child_obj() is in a device's instance_init() method, and the matching realize is in its realize() method. Perhaps a Coccinelle wizard could make it transform that pattern, but I'm just a bungler, and the best I can do is transforming the two separate parts separately: @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(OBJECT(child), true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(child, true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; @@ - qdev_init_nofail(DEVICE(child)); + sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; expression dev; @@ dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; identifier dev; @@ DeviceState *dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression parent, name, size, type; expression child; symbol true; @@ - sysbus_init_child_obj(parent, name, child, size, type); + sysbus_init_child_XXX(parent, name, child, size, type); @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type) + object_initialize_child(parent, propname, &child, type) This script is *unsound*: we need to manually verify init and realize conversions are properly paired. This commit has only the pairs where object_initialize_child()'s @child and sysbus_realize()'s @dev argument text match exactly within the same source file. Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
179 lines
6.0 KiB
C
179 lines
6.0 KiB
C
/*
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* ARM11MPCore internal peripheral emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/cpu/arm11mpcore.h"
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#include "hw/intc/realview_gic.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4
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static void mpcore_priv_set_irq(void *opaque, int irq, int level)
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{
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ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
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}
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static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
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{
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int i;
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SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
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DeviceState *gicdev = DEVICE(&s->gic);
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SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
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SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
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SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(scubusdev, 0));
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/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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* at 0x200, 0x300...
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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hwaddr offset = 0x100 + (i * 0x100);
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(gicbusdev, i + 1));
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}
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/* Add the regions for timer and watchdog for "current CPU" and
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* for each specific CPU.
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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hwaddr offset = 0x600 + i * 0x100;
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(timerbusdev, i));
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memory_region_add_subregion(&s->container, offset + 0x20,
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sysbus_mmio_get_region(wdtbusdev, i));
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}
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memory_region_add_subregion(&s->container, 0x1000,
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sysbus_mmio_get_region(gicbusdev, 0));
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/* Wire up the interrupt from each watchdog and timer.
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* For each core the timer is PPI 29 and the watchdog PPI 30.
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*/
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for (i = 0; i < s->num_cpu; i++) {
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int ppibase = (s->num_irq - 32) + i * 32;
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sysbus_connect_irq(timerbusdev, i,
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qdev_get_gpio_in(gicdev, ppibase + 29));
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sysbus_connect_irq(wdtbusdev, i,
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qdev_get_gpio_in(gicdev, ppibase + 30));
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}
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}
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static void mpcore_priv_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
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DeviceState *scudev = DEVICE(&s->scu);
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DeviceState *gicdev = DEVICE(&s->gic);
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DeviceState *mptimerdev = DEVICE(&s->mptimer);
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DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
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Error *err = NULL;
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qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
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sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
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qdev_prop_set_uint32(gicdev, "num-priority-bits",
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ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
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sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* Pass through outbound IRQ lines from the GIC */
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sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
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qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
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sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
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sysbus_realize(SYS_BUS_DEVICE(&s->wdtimer), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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mpcore_priv_map_setup(s);
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}
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static void mpcore_priv_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
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memory_region_init(&s->container, OBJECT(s),
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"mpcore-priv-container", 0x2000);
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sysbus_init_mmio(sbd, &s->container);
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object_initialize_child(obj, "scu", &s->scu, TYPE_ARM11_SCU);
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object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
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/* Request the legacy 11MPCore GIC behaviour: */
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
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object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER);
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object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER);
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}
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static Property mpcore_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
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/* The ARM11 MPCORE TRM says the on-chip controller may have
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* anything from 0 to 224 external interrupt IRQ lines (with another
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* 32 internal). We default to 32+32, which is the number provided by
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* the ARM11 MPCore test chip in the Realview Versatile Express
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* coretile. Other boards may differ and should set this property
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* appropriately. Some Linux kernels may not boot if the hardware
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* has more IRQ lines than the kernel expects.
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*/
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DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mpcore_priv_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mpcore_priv_realize;
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device_class_set_props(dc, mpcore_priv_properties);
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}
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static const TypeInfo mpcore_priv_info = {
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.name = TYPE_ARM11MPCORE_PRIV,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARM11MPCorePriveState),
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.instance_init = mpcore_priv_initfn,
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.class_init = mpcore_priv_class_init,
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};
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static void arm11mpcore_register_types(void)
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{
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type_register_static(&mpcore_priv_info);
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}
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type_init(arm11mpcore_register_types)
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