qemu/target/openrisc
Tim 'mithro' Ansell 356a2db3c6 target/openrisc: Implement EVBAR register
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.

The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).

Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).

Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-04-21 23:55:48 +09:00
..
cpu.c target/openrisc: Implement EVBAR register 2017-04-21 23:55:48 +09:00
cpu.h target/openrisc: Implement EVBAR register 2017-04-21 23:55:48 +09:00
exception_helper.c target/openrisc: Optimize for r0 being zero 2017-02-14 08:15:00 +11:00
exception.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
exception.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
fpu_helper.c target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
gdbstub.c target/openrisc: Tidy handling of delayed branches 2017-02-14 08:15:00 +11:00
helper.h target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
interrupt_helper.c target/openrisc: Tidy ppc/npc implementation 2017-02-14 08:15:00 +11:00
interrupt.c target/openrisc: Implement EVBAR register 2017-04-21 23:55:48 +09:00
machine.c target/openrisc: Tidy ppc/npc implementation 2017-02-14 08:15:00 +11:00
Makefile.objs target/openrisc: Streamline arithmetic and OVE 2017-02-14 08:14:59 +11:00
mmu_helper.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
mmu.c target/openrisc: Implement lwa, swa 2017-02-14 08:14:59 +11:00
sys_helper.c target/openrisc: Implement EVBAR register 2017-04-21 23:55:48 +09:00
translate.c target/openrisc: Optimize for r0 being zero 2017-02-14 08:15:00 +11:00