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793abe24aa
Add the differential clock input feature bit to the generated SPD data. Most guests don't seem to care but pegasos2 firmware version 1.2 checks for this bit and stops with unsupported module type error if it's not present. Since this feature is likely present on real memory modules add it in the general code rather than patching the generated SPD data in pegasos2 board only. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <19d42ade295d5297aa624a9eb757b8df18cf64d6.1626367844.git.balaton@eik.bme.hu> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
301 lines
9.1 KiB
C
301 lines
9.1 KiB
C
/*
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* QEMU SMBus EEPROM device
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*
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* Copyright (c) 2007 Arastra, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/i2c/i2c.h"
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#include "hw/i2c/smbus_slave.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "qom/object.h"
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//#define DEBUG
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#define TYPE_SMBUS_EEPROM "smbus-eeprom"
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OBJECT_DECLARE_SIMPLE_TYPE(SMBusEEPROMDevice, SMBUS_EEPROM)
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#define SMBUS_EEPROM_SIZE 256
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struct SMBusEEPROMDevice {
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SMBusDevice smbusdev;
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uint8_t data[SMBUS_EEPROM_SIZE];
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uint8_t *init_data;
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uint8_t offset;
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bool accessed;
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};
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static uint8_t eeprom_receive_byte(SMBusDevice *dev)
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{
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SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
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uint8_t *data = eeprom->data;
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uint8_t val = data[eeprom->offset++];
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eeprom->accessed = true;
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#ifdef DEBUG
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printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n",
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dev->i2c.address, val);
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#endif
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return val;
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}
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static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len)
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{
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SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
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uint8_t *data = eeprom->data;
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eeprom->accessed = true;
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#ifdef DEBUG
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printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n",
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dev->i2c.address, buf[0], buf[1]);
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#endif
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/* len is guaranteed to be > 0 */
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eeprom->offset = buf[0];
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buf++;
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len--;
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for (; len > 0; len--) {
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data[eeprom->offset] = *buf++;
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eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;
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}
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return 0;
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}
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static bool smbus_eeprom_vmstate_needed(void *opaque)
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{
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MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
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SMBusEEPROMDevice *eeprom = opaque;
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return (eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev)) &&
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!mc->smbus_no_migration_support;
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}
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static const VMStateDescription vmstate_smbus_eeprom = {
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.name = "smbus-eeprom",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = smbus_eeprom_vmstate_needed,
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.fields = (VMStateField[]) {
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VMSTATE_SMBUS_DEVICE(smbusdev, SMBusEEPROMDevice),
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VMSTATE_UINT8_ARRAY(data, SMBusEEPROMDevice, SMBUS_EEPROM_SIZE),
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VMSTATE_UINT8(offset, SMBusEEPROMDevice),
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VMSTATE_BOOL(accessed, SMBusEEPROMDevice),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* Reset the EEPROM contents to the initial state on a reset. This
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* isn't really how an EEPROM works, of course, but the general
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* principle of QEMU is to restore function on reset to what it would
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* be if QEMU was stopped and started.
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*
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* The proper thing to do would be to have a backing blockdev to hold
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* the contents and restore that on startup, and not do this on reset.
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* But until that time, act as if we had been stopped and restarted.
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*/
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static void smbus_eeprom_reset(DeviceState *dev)
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{
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SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
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memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE);
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eeprom->offset = 0;
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}
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static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
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{
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SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
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smbus_eeprom_reset(dev);
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if (eeprom->init_data == NULL) {
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error_setg(errp, "init_data cannot be NULL");
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}
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}
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static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass);
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dc->realize = smbus_eeprom_realize;
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dc->reset = smbus_eeprom_reset;
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sc->receive_byte = eeprom_receive_byte;
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sc->write_data = eeprom_write_data;
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dc->vmsd = &vmstate_smbus_eeprom;
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/* Reason: init_data */
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dc->user_creatable = false;
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}
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static const TypeInfo smbus_eeprom_info = {
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.name = TYPE_SMBUS_EEPROM,
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.parent = TYPE_SMBUS_DEVICE,
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.instance_size = sizeof(SMBusEEPROMDevice),
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.class_init = smbus_eeprom_class_initfn,
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};
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static void smbus_eeprom_register_types(void)
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{
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type_register_static(&smbus_eeprom_info);
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}
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type_init(smbus_eeprom_register_types)
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void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
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{
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DeviceState *dev;
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dev = qdev_new(TYPE_SMBUS_EEPROM);
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qdev_prop_set_uint8(dev, "address", address);
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/* FIXME: use an array of byte or block backend property? */
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SMBUS_EEPROM(dev)->init_data = eeprom_buf;
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qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal);
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}
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void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
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const uint8_t *eeprom_spd, int eeprom_spd_size)
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{
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int i;
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/* XXX: make this persistent */
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assert(nb_eeprom <= 8);
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uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);
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if (eeprom_spd_size > 0) {
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memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
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}
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for (i = 0; i < nb_eeprom; i++) {
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smbus_eeprom_init_one(smbus, 0x50 + i,
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eeprom_buf + (i * SMBUS_EEPROM_SIZE));
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}
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}
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/* Generate SDRAM SPD EEPROM data describing a module of type and size */
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uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size)
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{
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uint8_t *spd;
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uint8_t nbanks;
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uint16_t density;
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uint32_t size;
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int min_log2, max_log2, sz_log2;
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int i;
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switch (type) {
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case SDR:
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min_log2 = 2;
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max_log2 = 9;
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break;
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case DDR:
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min_log2 = 5;
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max_log2 = 12;
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break;
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case DDR2:
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min_log2 = 7;
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max_log2 = 14;
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break;
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default:
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g_assert_not_reached();
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}
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size = ram_size >> 20; /* work in terms of megabytes */
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sz_log2 = 31 - clz32(size);
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size = 1U << sz_log2;
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assert(ram_size == size * MiB);
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assert(sz_log2 >= min_log2);
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nbanks = 1;
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while (sz_log2 > max_log2 && nbanks < 8) {
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sz_log2--;
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nbanks *= 2;
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}
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assert(size == (1ULL << sz_log2) * nbanks);
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/* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */
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if (nbanks == 1 && sz_log2 > min_log2) {
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sz_log2--;
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nbanks++;
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}
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density = 1ULL << (sz_log2 - 2);
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switch (type) {
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case DDR2:
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density = (density & 0xe0) | (density >> 8 & 0x1f);
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break;
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case DDR:
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density = (density & 0xf8) | (density >> 8 & 0x07);
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break;
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case SDR:
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default:
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density &= 0xff;
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break;
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}
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spd = g_malloc0(256);
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spd[0] = 128; /* data bytes in EEPROM */
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spd[1] = 8; /* log2 size of EEPROM */
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spd[2] = type;
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spd[3] = 13; /* row address bits */
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spd[4] = 10; /* column address bits */
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spd[5] = (type == DDR2 ? nbanks - 1 : nbanks);
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spd[6] = 64; /* module data width */
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/* reserved / data width high */
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spd[8] = 4; /* interface voltage level */
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spd[9] = 0x25; /* highest CAS latency */
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spd[10] = 1; /* access time */
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/* DIMM configuration 0 = non-ECC */
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spd[12] = 0x82; /* refresh requirements */
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spd[13] = 8; /* primary SDRAM width */
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/* ECC SDRAM width */
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spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */
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spd[16] = 12; /* burst lengths supported */
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spd[17] = 4; /* banks per SDRAM device */
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spd[18] = 12; /* ~CAS latencies supported */
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spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */
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spd[20] = 2; /* DIMM type / ~WE latencies */
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spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */
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/* memory chip features */
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spd[23] = 0x12; /* clock cycle time @ medium CAS latency */
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/* data access time */
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/* clock cycle time @ short CAS latency */
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/* data access time */
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spd[27] = 20; /* min. row precharge time */
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spd[28] = 15; /* min. row active row delay */
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spd[29] = 20; /* min. ~RAS to ~CAS delay */
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spd[30] = 45; /* min. active to precharge time */
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spd[31] = density;
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spd[32] = 20; /* addr/cmd setup time */
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spd[33] = 8; /* addr/cmd hold time */
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spd[34] = 20; /* data input setup time */
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spd[35] = 8; /* data input hold time */
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/* checksum */
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for (i = 0; i < 63; i++) {
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spd[63] += spd[i];
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}
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return spd;
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}
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