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00b941e581
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helpers
cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
Prepares for changing cpu_memory_rw_debug() argument to CPUState.
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
243 lines
6.7 KiB
C
243 lines
6.7 KiB
C
/*
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* OpenRISC MMU.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw)
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{
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return TLBRET_MATCH;
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}
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int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw)
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{
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & ITLB_MASK;
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int right = 0;
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if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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}
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if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) {
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return TLBRET_INVALID;
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}
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if (cpu->env.sr & SR_SM) { /* supervisor mode */
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if (cpu->env.tlb->itlb[0][idx].tr & SXE) {
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right |= PAGE_EXEC;
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}
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} else {
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if (cpu->env.tlb->itlb[0][idx].tr & UXE) {
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right |= PAGE_EXEC;
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}
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}
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if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
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return TLBRET_BADADDR;
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}
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*physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) |
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(address & (TARGET_PAGE_SIZE-1));
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*prot = right;
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return TLBRET_MATCH;
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}
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int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address, int rw)
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{
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & DTLB_MASK;
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int right = 0;
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if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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}
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if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) {
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return TLBRET_INVALID;
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}
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if (cpu->env.sr & SR_SM) { /* supervisor mode */
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if (cpu->env.tlb->dtlb[0][idx].tr & SRE) {
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right |= PAGE_READ;
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}
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if (cpu->env.tlb->dtlb[0][idx].tr & SWE) {
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right |= PAGE_WRITE;
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}
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} else {
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if (cpu->env.tlb->dtlb[0][idx].tr & URE) {
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right |= PAGE_READ;
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}
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if (cpu->env.tlb->dtlb[0][idx].tr & UWE) {
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right |= PAGE_WRITE;
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}
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}
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if ((rw & 0) && ((right & PAGE_READ) == 0)) {
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return TLBRET_BADADDR;
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}
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if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
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return TLBRET_BADADDR;
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}
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*physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) |
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(address & (TARGET_PAGE_SIZE-1));
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*prot = right;
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return TLBRET_MATCH;
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}
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static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot, target_ulong address,
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int rw)
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{
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int ret = TLBRET_MATCH;
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/* [0x0000--0x2000]: unmapped */
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if (address < 0x2000 && (cpu->env.sr & SR_SM)) {
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return ret;
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}
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if (rw == 2) { /* ITLB */
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*physical = 0;
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ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
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prot, address, rw);
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} else { /* DTLB */
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ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical,
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prot, address, rw);
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}
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return ret;
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}
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#endif
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static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
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target_ulong address,
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int rw, int tlb_error)
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{
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int exception = 0;
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switch (tlb_error) {
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default:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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#ifndef CONFIG_USER_ONLY
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case TLBRET_BADADDR:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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case TLBRET_INVALID:
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw == 2) {
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exception = EXCP_ITLBMISS;
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} else {
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exception = EXCP_DTLBMISS;
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}
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break;
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#endif
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}
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cpu->env.exception_index = exception;
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cpu->env.eear = address;
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}
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#ifndef CONFIG_USER_ONLY
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int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
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target_ulong address, int rw, int mmu_idx)
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{
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int ret = 0;
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hwaddr physical = 0;
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int prot = 0;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
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address, rw);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(env, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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} else if (ret < 0) {
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cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
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ret = 1;
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}
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return ret;
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}
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#else
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int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
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target_ulong address, int rw, int mmu_idx)
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{
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int ret = 0;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
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ret = 1;
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return ret;
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}
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#endif
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#ifndef CONFIG_USER_ONLY
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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hwaddr phys_addr;
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int prot;
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if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
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return -1;
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}
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return phys_addr;
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}
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void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
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{
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cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext));
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cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
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cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
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}
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#endif
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