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e7424abc20
Record trap_arg{0,1,2} for the linux-user signal frame. Raise SIGBUS directly from cpu_loop_exit_sigbus, which means we can remove the code for EXCP_UNALIGN in cpu_loop. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
287 lines
8.3 KiB
C
287 lines
8.3 KiB
C
/*
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* QEMU Alpha CPU
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*
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
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{
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AlphaCPU *cpu = ALPHA_CPU(cs);
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cpu->env.pc = value;
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}
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static bool alpha_cpu_has_work(CPUState *cs)
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{
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/* Here we are checking to see if the CPU should wake up from HALT.
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We will have gotten into this state only for WTINT from PALmode. */
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/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
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asleep even if (some) interrupts have been asserted. For now,
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assume that if a CPU really wants to stay asleep, it will mask
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interrupts at the chipset level, which will prevent these bits
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from being set in the first place. */
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return cs->interrupt_request & (CPU_INTERRUPT_HARD
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| CPU_INTERRUPT_TIMER
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| CPU_INTERRUPT_SMP
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| CPU_INTERRUPT_MCHK);
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}
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static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_alpha_ev6;
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info->print_insn = print_insn_alpha;
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}
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static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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acc->parent_realize(dev, errp);
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}
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static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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qemu_printf(" %s\n", object_class_get_name(oc));
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}
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void alpha_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_ALPHA_CPU, false);
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qemu_printf("Available CPUs:\n");
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g_slist_foreach(list, alpha_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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/* Models */
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typedef struct AlphaCPUAlias {
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const char *alias;
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const char *typename;
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} AlphaCPUAlias;
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static const AlphaCPUAlias alpha_cpu_aliases[] = {
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{ "21064", ALPHA_CPU_TYPE_NAME("ev4") },
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{ "21164", ALPHA_CPU_TYPE_NAME("ev5") },
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{ "21164a", ALPHA_CPU_TYPE_NAME("ev56") },
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{ "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
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{ "21264", ALPHA_CPU_TYPE_NAME("ev6") },
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{ "21264a", ALPHA_CPU_TYPE_NAME("ev67") },
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};
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static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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int i;
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oc = object_class_by_name(cpu_model);
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if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
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!object_class_is_abstract(oc)) {
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return oc;
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}
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for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
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if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
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oc = object_class_by_name(alpha_cpu_aliases[i].typename);
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assert(oc != NULL && !object_class_is_abstract(oc));
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return oc;
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}
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}
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typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && object_class_is_abstract(oc)) {
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oc = NULL;
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}
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/* TODO: remove match everything nonsense */
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/* Default to ev67; no reason not to emulate insns by default. */
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if (!oc) {
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oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
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}
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return oc;
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}
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static void ev4_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->implver = IMPLVER_2106x;
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}
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static void ev5_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->implver = IMPLVER_21164;
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}
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static void ev56_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->amask |= AMASK_BWX;
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}
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static void pca56_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->amask |= AMASK_MVI;
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}
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static void ev6_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->implver = IMPLVER_21264;
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env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
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}
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static void ev67_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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env->amask |= AMASK_CIX | AMASK_PREFETCH;
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}
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static void alpha_cpu_initfn(Object *obj)
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{
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AlphaCPU *cpu = ALPHA_CPU(obj);
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CPUAlphaState *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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env->lock_addr = -1;
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#if defined(CONFIG_USER_ONLY)
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env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
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cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
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| FPCR_UNFD | FPCR_INED | FPCR_DNOD
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| FPCR_DYN_NORMAL) << 32);
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#else
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env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps alpha_sysemu_ops = {
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.get_phys_page_debug = alpha_cpu_get_phys_page_debug,
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};
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#endif
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps alpha_tcg_ops = {
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.initialize = alpha_translate_init,
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#ifdef CONFIG_USER_ONLY
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.record_sigsegv = alpha_cpu_record_sigsegv,
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.record_sigbus = alpha_cpu_record_sigbus,
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#else
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.tlb_fill = alpha_cpu_tlb_fill,
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.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
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.do_interrupt = alpha_cpu_do_interrupt,
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.do_transaction_failed = alpha_cpu_do_transaction_failed,
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.do_unaligned_access = alpha_cpu_do_unaligned_access,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void alpha_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, alpha_cpu_realizefn,
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&acc->parent_realize);
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cc->class_by_name = alpha_cpu_class_by_name;
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cc->has_work = alpha_cpu_has_work;
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cc->dump_state = alpha_cpu_dump_state;
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cc->set_pc = alpha_cpu_set_pc;
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cc->gdb_read_register = alpha_cpu_gdb_read_register;
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cc->gdb_write_register = alpha_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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dc->vmsd = &vmstate_alpha_cpu;
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cc->sysemu_ops = &alpha_sysemu_ops;
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#endif
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cc->disas_set_info = alpha_cpu_disas_set_info;
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cc->tcg_ops = &alpha_tcg_ops;
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cc->gdb_num_core_regs = 67;
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}
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#define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
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{ \
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.parent = base_type, \
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.instance_init = initfn, \
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.name = ALPHA_CPU_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo alpha_cpu_type_infos[] = {
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{
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.name = TYPE_ALPHA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(AlphaCPU),
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.instance_init = alpha_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(AlphaCPUClass),
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.class_init = alpha_cpu_class_init,
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},
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DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
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pca56_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn),
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DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL),
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};
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DEFINE_TYPES(alpha_cpu_type_infos)
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