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2a6e32dd46
qemu/target-mips
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Aurelien Jarno 2a6e32dd46 target-mips: make CP0_LLAddr register CPU dependent 
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
..
cpu.h target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00
exec.h qemu: per-arch cpu_has_work (Marcelo Tosatti) 2009-04-24 18:03:20 +00:00
helper.c Revert "Get rid of _t suffix" 2009-10-01 16:12:16 -05:00
helper.h target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00
machine.c target-mips: rename CP0_LLAddr into lladdr 2009-11-22 14:12:13 +01:00
mips-defs.h Hardware convenience library 2009-05-19 16:17:58 +01:00
op_helper.c target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00
TODO Move the active FPU registers into env again, and use more TCG registers 2008-09-18 11:57:27 +00:00
translate_init.c target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00
translate.c target-mips: make CP0_LLAddr register CPU dependent 2009-11-22 14:12:19 +01:00