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19f4ed3652
Many files include qemu/log.h without needing it. Remove the superfluous include statements. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210328054833.2351597-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
360 lines
9.0 KiB
C
360 lines
9.0 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Amit Tomar, <Amit.Tomar@freescale.com>
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*
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* Description:
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* This file is derived from IMX I2C controller,
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* by Jean-Christophe DUBOIS .
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*
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* Thanks to Scott Wood and Alexander Graf for their kind help on this.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2 or later,
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* as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/i2c/i2c.h"
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#include "hw/irq.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qom/object.h"
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/* #define DEBUG_I2C */
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#ifdef DEBUG_I2C
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "mpc_i2c[%s]: " fmt, __func__, ## __VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define TYPE_MPC_I2C "mpc-i2c"
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OBJECT_DECLARE_SIMPLE_TYPE(MPCI2CState, MPC_I2C)
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#define MPC_I2C_ADR 0x00
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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#define MPC_I2C_DR 0x10
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#define MPC_I2C_DFSRR 0x14
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#define CCR_MEN (1 << 7)
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#define CCR_MIEN (1 << 6)
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#define CCR_MSTA (1 << 5)
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#define CCR_MTX (1 << 4)
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#define CCR_TXAK (1 << 3)
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#define CCR_RSTA (1 << 2)
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#define CCR_BCST (1 << 0)
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#define CSR_MCF (1 << 7)
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#define CSR_MAAS (1 << 6)
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#define CSR_MBB (1 << 5)
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#define CSR_MAL (1 << 4)
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#define CSR_SRW (1 << 2)
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#define CSR_MIF (1 << 1)
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#define CSR_RXAK (1 << 0)
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#define CADR_MASK 0xFE
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#define CFDR_MASK 0x3F
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#define CCR_MASK 0xFC
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#define CSR_MASK 0xED
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#define CDR_MASK 0xFF
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#define CYCLE_RESET 0xFF
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struct MPCI2CState {
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SysBusDevice parent_obj;
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I2CBus *bus;
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qemu_irq irq;
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MemoryRegion iomem;
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uint8_t address;
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uint8_t adr;
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uint8_t fdr;
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uint8_t cr;
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uint8_t sr;
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uint8_t dr;
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uint8_t dfssr;
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};
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static bool mpc_i2c_is_enabled(MPCI2CState *s)
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{
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return s->cr & CCR_MEN;
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}
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static bool mpc_i2c_is_master(MPCI2CState *s)
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{
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return s->cr & CCR_MSTA;
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}
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static bool mpc_i2c_direction_is_tx(MPCI2CState *s)
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{
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return s->cr & CCR_MTX;
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}
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static bool mpc_i2c_irq_pending(MPCI2CState *s)
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{
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return s->sr & CSR_MIF;
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}
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static bool mpc_i2c_irq_is_enabled(MPCI2CState *s)
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{
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return s->cr & CCR_MIEN;
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}
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static void mpc_i2c_reset(DeviceState *dev)
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{
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MPCI2CState *i2c = MPC_I2C(dev);
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i2c->address = 0xFF;
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i2c->adr = 0x00;
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i2c->fdr = 0x00;
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i2c->cr = 0x00;
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i2c->sr = 0x81;
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i2c->dr = 0x00;
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}
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static void mpc_i2c_irq(MPCI2CState *s)
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{
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bool irq_active = false;
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if (mpc_i2c_is_enabled(s) && mpc_i2c_irq_is_enabled(s)
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&& mpc_i2c_irq_pending(s)) {
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irq_active = true;
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}
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if (irq_active) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void mpc_i2c_soft_reset(MPCI2CState *s)
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{
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/* This is a soft reset. ADR is preserved during soft resets */
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uint8_t adr = s->adr;
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mpc_i2c_reset(DEVICE(s));
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s->adr = adr;
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}
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static void mpc_i2c_address_send(MPCI2CState *s)
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{
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/* if returns non zero slave address is not right */
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if (i2c_start_transfer(s->bus, s->dr >> 1, s->dr & (0x01))) {
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s->sr |= CSR_RXAK;
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} else {
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s->address = s->dr;
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s->sr &= ~CSR_RXAK;
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s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */
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s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */
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mpc_i2c_irq(s);
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}
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}
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static void mpc_i2c_data_send(MPCI2CState *s)
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{
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if (i2c_send(s->bus, s->dr)) {
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/* End of transfer */
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s->sr |= CSR_RXAK;
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i2c_end_transfer(s->bus);
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} else {
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s->sr &= ~CSR_RXAK;
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s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */
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s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */
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mpc_i2c_irq(s);
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}
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}
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static void mpc_i2c_data_recive(MPCI2CState *s)
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{
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int ret;
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/* get the next byte */
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ret = i2c_recv(s->bus);
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if (ret >= 0) {
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s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */
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s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */
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mpc_i2c_irq(s);
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} else {
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DPRINTF("read failed for device");
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ret = 0xff;
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}
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s->dr = ret;
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}
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static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size)
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{
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MPCI2CState *s = opaque;
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uint8_t value;
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switch (addr) {
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case MPC_I2C_ADR:
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value = s->adr;
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break;
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case MPC_I2C_FDR:
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value = s->fdr;
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break;
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case MPC_I2C_CR:
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value = s->cr;
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break;
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case MPC_I2C_SR:
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value = s->sr;
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break;
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case MPC_I2C_DR:
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value = s->dr;
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if (mpc_i2c_is_master(s)) { /* master mode */
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if (mpc_i2c_direction_is_tx(s)) {
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DPRINTF("MTX is set not in recv mode\n");
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} else {
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mpc_i2c_data_recive(s);
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}
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}
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break;
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default:
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value = 0;
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DPRINTF("ERROR: Bad read addr 0x%x\n", (unsigned int)addr);
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break;
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}
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DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__,
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addr, value);
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return (uint64_t)value;
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}
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static void mpc_i2c_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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MPCI2CState *s = opaque;
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DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__,
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addr, value);
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switch (addr) {
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case MPC_I2C_ADR:
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s->adr = value & CADR_MASK;
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break;
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case MPC_I2C_FDR:
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s->fdr = value & CFDR_MASK;
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break;
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case MPC_I2C_CR:
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if (mpc_i2c_is_enabled(s) && ((value & CCR_MEN) == 0)) {
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mpc_i2c_soft_reset(s);
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break;
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}
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/* normal write */
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s->cr = value & CCR_MASK;
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if (mpc_i2c_is_master(s)) { /* master mode */
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/* set the bus to busy after master is set as per RM */
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s->sr |= CSR_MBB;
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} else {
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/* bus is not busy anymore */
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s->sr &= ~CSR_MBB;
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/* Reset the address for fresh write/read cycle */
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if (s->address != CYCLE_RESET) {
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i2c_end_transfer(s->bus);
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s->address = CYCLE_RESET;
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}
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}
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/* For restart end the onging transfer */
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if (s->cr & CCR_RSTA) {
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if (s->address != CYCLE_RESET) {
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s->address = CYCLE_RESET;
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i2c_end_transfer(s->bus);
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s->cr &= ~CCR_RSTA;
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}
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}
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break;
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case MPC_I2C_SR:
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s->sr = value & CSR_MASK;
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/* Lower the interrupt */
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if (!(s->sr & CSR_MIF) || !(s->sr & CSR_MAL)) {
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mpc_i2c_irq(s);
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}
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break;
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case MPC_I2C_DR:
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/* if the device is not enabled, nothing to do */
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if (!mpc_i2c_is_enabled(s)) {
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break;
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}
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s->dr = value & CDR_MASK;
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if (mpc_i2c_is_master(s)) { /* master mode */
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if (s->address == CYCLE_RESET) {
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mpc_i2c_address_send(s);
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} else {
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mpc_i2c_data_send(s);
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}
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}
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break;
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case MPC_I2C_DFSRR:
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s->dfssr = value;
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break;
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default:
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DPRINTF("ERROR: Bad write addr 0x%x\n", (unsigned int)addr);
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break;
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}
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}
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static const MemoryRegionOps i2c_ops = {
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.read = mpc_i2c_read,
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.write = mpc_i2c_write,
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.valid.max_access_size = 1,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription mpc_i2c_vmstate = {
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.name = TYPE_MPC_I2C,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(address, MPCI2CState),
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VMSTATE_UINT8(adr, MPCI2CState),
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VMSTATE_UINT8(fdr, MPCI2CState),
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VMSTATE_UINT8(cr, MPCI2CState),
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VMSTATE_UINT8(sr, MPCI2CState),
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VMSTATE_UINT8(dr, MPCI2CState),
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VMSTATE_UINT8(dfssr, MPCI2CState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mpc_i2c_realize(DeviceState *dev, Error **errp)
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{
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MPCI2CState *i2c = MPC_I2C(dev);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &i2c->irq);
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memory_region_init_io(&i2c->iomem, OBJECT(i2c), &i2c_ops, i2c,
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"mpc-i2c", 0x14);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &i2c->iomem);
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i2c->bus = i2c_init_bus(dev, "i2c");
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}
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static void mpc_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &mpc_i2c_vmstate ;
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dc->reset = mpc_i2c_reset;
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dc->realize = mpc_i2c_realize;
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dc->desc = "MPC I2C Controller";
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}
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static const TypeInfo mpc_i2c_type_info = {
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.name = TYPE_MPC_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MPCI2CState),
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.class_init = mpc_i2c_class_init,
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};
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static void mpc_i2c_register_types(void)
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{
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type_register_static(&mpc_i2c_type_info);
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}
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type_init(mpc_i2c_register_types)
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