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d2623129a7
The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
359 lines
12 KiB
C
359 lines
12 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER8) PHB3 model
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*
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* Copyright (c) 2014-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "qemu/log.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/fdt.h"
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#include "hw/pci-host/pnv_phb3_regs.h"
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#include "hw/pci-host/pnv_phb3.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include <libfdt.h>
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#define phb3_pbcq_error(pbcq, fmt, ...) \
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qemu_log_mask(LOG_GUEST_ERROR, "phb3_pbcq[%d:%d]: " fmt "\n", \
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(pbcq)->phb->chip_id, (pbcq)->phb->phb_id, ## __VA_ARGS__)
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static uint64_t pnv_pbcq_nest_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t offset = addr >> 3;
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return pbcq->nest_regs[offset];
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}
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static uint64_t pnv_pbcq_pci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t offset = addr >> 3;
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return pbcq->pci_regs[offset];
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}
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static uint64_t pnv_pbcq_spci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t offset = addr >> 3;
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if (offset == PBCQ_SPCI_ASB_DATA) {
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return pnv_phb3_reg_read(pbcq->phb,
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pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR], 8);
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}
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return pbcq->spci_regs[offset];
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}
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static void pnv_pbcq_update_map(PnvPBCQState *pbcq)
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{
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uint64_t bar_en = pbcq->nest_regs[PBCQ_NEST_BAR_EN];
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uint64_t bar, mask, size;
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/*
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* NOTE: This will really not work well if those are remapped
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* after the PHB has created its sub regions. We could do better
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* if we had a way to resize regions but we don't really care
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* that much in practice as the stuff below really only happens
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* once early during boot
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*/
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/* Handle unmaps */
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if (memory_region_is_mapped(&pbcq->mmbar0) &&
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!(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
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memory_region_del_subregion(get_system_memory(), &pbcq->mmbar0);
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}
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if (memory_region_is_mapped(&pbcq->mmbar1) &&
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!(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
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memory_region_del_subregion(get_system_memory(), &pbcq->mmbar1);
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}
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if (memory_region_is_mapped(&pbcq->phbbar) &&
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!(bar_en & PBCQ_NEST_BAR_EN_PHB)) {
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memory_region_del_subregion(get_system_memory(), &pbcq->phbbar);
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}
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/* Update PHB */
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pnv_phb3_update_regions(pbcq->phb);
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/* Handle maps */
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if (!memory_region_is_mapped(&pbcq->mmbar0) &&
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(bar_en & PBCQ_NEST_BAR_EN_MMIO0)) {
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bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14;
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mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0];
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size = ((~mask) >> 14) + 1;
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memory_region_init(&pbcq->mmbar0, OBJECT(pbcq), "pbcq-mmio0", size);
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memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar0);
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pbcq->mmio0_base = bar;
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pbcq->mmio0_size = size;
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}
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if (!memory_region_is_mapped(&pbcq->mmbar1) &&
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(bar_en & PBCQ_NEST_BAR_EN_MMIO1)) {
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bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14;
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mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1];
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size = ((~mask) >> 14) + 1;
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memory_region_init(&pbcq->mmbar1, OBJECT(pbcq), "pbcq-mmio1", size);
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memory_region_add_subregion(get_system_memory(), bar, &pbcq->mmbar1);
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pbcq->mmio1_base = bar;
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pbcq->mmio1_size = size;
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}
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if (!memory_region_is_mapped(&pbcq->phbbar)
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&& (bar_en & PBCQ_NEST_BAR_EN_PHB)) {
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bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14;
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size = 0x1000;
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memory_region_init(&pbcq->phbbar, OBJECT(pbcq), "pbcq-phb", size);
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memory_region_add_subregion(get_system_memory(), bar, &pbcq->phbbar);
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}
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/* Update PHB */
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pnv_phb3_update_regions(pbcq->phb);
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}
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static void pnv_pbcq_nest_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PBCQ_NEST_MMIO_BAR0:
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case PBCQ_NEST_MMIO_BAR1:
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case PBCQ_NEST_MMIO_MASK0:
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case PBCQ_NEST_MMIO_MASK1:
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if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] &
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(PBCQ_NEST_BAR_EN_MMIO0 |
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PBCQ_NEST_BAR_EN_MMIO1)) {
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phb3_pbcq_error(pbcq, "Changing enabled BAR unsupported");
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}
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pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull;
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break;
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case PBCQ_NEST_PHB_BAR:
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if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & PBCQ_NEST_BAR_EN_PHB) {
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phb3_pbcq_error(pbcq, "Changing enabled BAR unsupported");
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}
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pbcq->nest_regs[reg] = val & 0xfffffffffc000000ull;
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break;
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case PBCQ_NEST_BAR_EN:
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pbcq->nest_regs[reg] = val & 0xf800000000000000ull;
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pnv_pbcq_update_map(pbcq);
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pnv_phb3_remap_irqs(pbcq->phb);
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break;
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case PBCQ_NEST_IRSN_COMPARE:
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case PBCQ_NEST_IRSN_MASK:
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pbcq->nest_regs[reg] = val & PBCQ_NEST_IRSN_COMP;
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pnv_phb3_remap_irqs(pbcq->phb);
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break;
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case PBCQ_NEST_LSI_SRC_ID:
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pbcq->nest_regs[reg] = val & PBCQ_NEST_LSI_SRC;
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pnv_phb3_remap_irqs(pbcq->phb);
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break;
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default:
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phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
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addr, val);
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}
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}
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static void pnv_pbcq_pci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PBCQ_PCI_BAR2:
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pbcq->pci_regs[reg] = val & 0xfffffffffc000000ull;
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pnv_pbcq_update_map(pbcq);
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break;
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default:
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phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
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addr, val);
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}
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}
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static void pnv_pbcq_spci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PBCQ_SPCI_ASB_ADDR:
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pbcq->spci_regs[reg] = val & 0xfff;
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break;
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case PBCQ_SPCI_ASB_STATUS:
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pbcq->spci_regs[reg] &= ~val;
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break;
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case PBCQ_SPCI_ASB_DATA:
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pnv_phb3_reg_write(pbcq->phb, pbcq->spci_regs[PBCQ_SPCI_ASB_ADDR],
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val, 8);
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break;
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case PBCQ_SPCI_AIB_CAPP_EN:
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case PBCQ_SPCI_CAPP_SEC_TMR:
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break;
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default:
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phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__,
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addr, val);
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}
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}
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static const MemoryRegionOps pnv_pbcq_nest_xscom_ops = {
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.read = pnv_pbcq_nest_xscom_read,
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.write = pnv_pbcq_nest_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static const MemoryRegionOps pnv_pbcq_pci_xscom_ops = {
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.read = pnv_pbcq_pci_xscom_read,
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.write = pnv_pbcq_pci_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static const MemoryRegionOps pnv_pbcq_spci_xscom_ops = {
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.read = pnv_pbcq_spci_xscom_read,
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.write = pnv_pbcq_spci_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_pbcq_default_bars(PnvPBCQState *pbcq)
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{
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uint64_t mm0, mm1, reg;
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PnvPHB3 *phb = pbcq->phb;
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mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id +
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0x1000000000ull * phb->phb_id;
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mm1 = 0x3ff8000000000ull + 0x0200000000ull * phb->chip_id +
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0x0080000000ull * phb->phb_id;
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reg = 0x3fffe40000000ull + 0x0000400000ull * phb->chip_id +
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0x0000100000ull * phb->phb_id;
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pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] = mm0 << 14;
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pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] = mm1 << 14;
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pbcq->nest_regs[PBCQ_NEST_PHB_BAR] = reg << 14;
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pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0] = 0x3fff000000000ull << 14;
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pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1] = 0x3ffff80000000ull << 14;
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pbcq->pci_regs[PBCQ_PCI_BAR2] = reg << 14;
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}
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static void pnv_pbcq_realize(DeviceState *dev, Error **errp)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(dev);
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PnvPHB3 *phb;
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char name[32];
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assert(pbcq->phb);
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phb = pbcq->phb;
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/* TODO: Fix OPAL to do that: establish default BAR values */
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pnv_pbcq_default_bars(pbcq);
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/* Initialize the XSCOM region for the PBCQ registers */
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snprintf(name, sizeof(name), "xscom-pbcq-nest-%d.%d",
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phb->chip_id, phb->phb_id);
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pnv_xscom_region_init(&pbcq->xscom_nest_regs, OBJECT(dev),
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&pnv_pbcq_nest_xscom_ops, pbcq, name,
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PNV_XSCOM_PBCQ_NEST_SIZE);
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snprintf(name, sizeof(name), "xscom-pbcq-pci-%d.%d",
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phb->chip_id, phb->phb_id);
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pnv_xscom_region_init(&pbcq->xscom_pci_regs, OBJECT(dev),
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&pnv_pbcq_pci_xscom_ops, pbcq, name,
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PNV_XSCOM_PBCQ_PCI_SIZE);
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snprintf(name, sizeof(name), "xscom-pbcq-spci-%d.%d",
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phb->chip_id, phb->phb_id);
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pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev),
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&pnv_pbcq_spci_xscom_ops, pbcq, name,
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PNV_XSCOM_PBCQ_SPCI_SIZE);
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}
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static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int xscom_offset)
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{
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const char compat[] = "ibm,power8-pbcq";
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PnvPHB3 *phb = PNV_PBCQ(dev)->phb;
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char *name;
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int offset;
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uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id;
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uint32_t reg[] = {
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cpu_to_be32(lpc_pcba),
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cpu_to_be32(PNV_XSCOM_PBCQ_NEST_SIZE),
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cpu_to_be32(PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id),
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cpu_to_be32(PNV_XSCOM_PBCQ_PCI_SIZE),
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cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id),
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cpu_to_be32(PNV_XSCOM_PBCQ_SPCI_SIZE)
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};
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name = g_strdup_printf("pbcq@%x", lpc_pcba);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,phb-index", phb->phb_id)));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", phb->chip_id)));
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_FDT((fdt_setprop(fdt, offset, "compatible", compat,
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sizeof(compat))));
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return 0;
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}
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static void phb3_pbcq_instance_init(Object *obj)
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{
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PnvPBCQState *pbcq = PNV_PBCQ(obj);
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object_property_add_link(obj, "phb", TYPE_PNV_PHB3,
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(Object **)&pbcq->phb,
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object_property_allow_set_link,
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OBJ_PROP_LINK_STRONG);
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}
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static void pnv_pbcq_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
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xdc->dt_xscom = pnv_pbcq_dt_xscom;
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dc->realize = pnv_pbcq_realize;
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dc->user_creatable = false;
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}
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static const TypeInfo pnv_pbcq_type_info = {
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.name = TYPE_PNV_PBCQ,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvPBCQState),
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.instance_init = phb3_pbcq_instance_init,
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.class_init = pnv_pbcq_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PNV_XSCOM_INTERFACE },
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{ }
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}
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};
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static void pnv_pbcq_register_types(void)
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{
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type_register_static(&pnv_pbcq_type_info);
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}
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type_init(pnv_pbcq_register_types)
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