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2152e08ad1
This tx timer implementation is flawed. Despite the controller attempting to time the guest visable assertion of the TX-empty status bit (and corresponding interrupt) the controller is still transmitting characters instantaneously. There is also no sense of multiple character delay. The only side effect of this timer is assertion of tx-empty status. So just remove the timer completely and hold tx-empty as permanently asserted (its reset status). This matches the actual behaviour of instantaneous transmission. While we are VMSD version bumping, add the tx_fifo as device state to prepare for upcomming TxFIFO flow control. Implement the interrupt generation logic for the TxFIFO occupancy. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7a208a7eb8d79d6429fe28b1396c3104371807b2.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
cadence_uart.c | ||
debugcon.c | ||
digic-uart.c | ||
escc.c | ||
etraxfs_ser.c | ||
exynos4210_uart.c | ||
grlib_apbuart.c | ||
imx_serial.c | ||
ipack.c | ||
ipack.h | ||
ipoctal232.c | ||
lm32_juart.c | ||
lm32_uart.c | ||
Makefile.objs | ||
mcf_uart.c | ||
milkymist-uart.c | ||
omap_uart.c | ||
parallel.c | ||
pl011.c | ||
sclpconsole-lm.c | ||
sclpconsole.c | ||
serial-isa.c | ||
serial-pci.c | ||
serial.c | ||
sh_serial.c | ||
spapr_vty.c | ||
tpci200.c | ||
virtio-console.c | ||
virtio-serial-bus.c | ||
xen_console.c | ||
xilinx_uartlite.c |