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-----BEGIN PGP SIGNATURE----- iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmJhYIscHG1hcmNhbmRy ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5W0jD/43n8PL2cv42lq6OaIS OYN9vfW9xgA9THZiUH4xEHYreZh+KofmY1PbJn1n7q+v6DecBiqM4fZr1LY8X3PM xRUH0l4gjXwYwX2cSSo5UTZ/PF248Uoo3tUE3vgMFkYghHMjKcTtaSkYEPGHf2nR t3m1qLG9w9YPhVg7PNCntjUKi+w2TtcrRVzP7V7XyFc1HrAoT0ys6KaBBrXMbcjz SxTRbcwSq+6aPjQIn0RWp8Hp1HkdNjegB98dkyqRLlVaugHZWPYDXDQTgVziQlX8 dU8YrlvTOtDWwsNP6awWnW6/IjKuJjGR0wT3QKwi8JAZ0YV3egwEKoQRUAyHtnn2 FkSMYgmJcF0ai1aIJFAx+3PIzCfS49lKXA0t303DtY3hRR9JKGMwaV2do9Wm2irt o7T1lKKN7R7R8Q3U4OsatYMYm7KYL07NEDiQCPloGvCo27ezkAWCKXAw1mRUkxKF jKwJPcnOUq21Jp6tpjsR8ifSw70jBSEWQSGqhXnDhZhx2C2/Qqkg2I8DagLiPger kYxbQ13LTG0R25YHa1r3UmzuD+HpZOM8XoLJc5yun/1UrwyR9ghHrOoxkSnRT2Ks QFn//xQ2SzUnGBNzNSMfTk8vzludxSWfFnOjkviF6E2Elnw3p8f/kOQRAft5dMBY ftgoy2yLone3HpKfjuOriicIzg== =0GLo -----END PGP SIGNATURE----- Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging Misc cleanups # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmJhYIscHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5W0jD/43n8PL2cv42lq6OaIS # OYN9vfW9xgA9THZiUH4xEHYreZh+KofmY1PbJn1n7q+v6DecBiqM4fZr1LY8X3PM # xRUH0l4gjXwYwX2cSSo5UTZ/PF248Uoo3tUE3vgMFkYghHMjKcTtaSkYEPGHf2nR # t3m1qLG9w9YPhVg7PNCntjUKi+w2TtcrRVzP7V7XyFc1HrAoT0ys6KaBBrXMbcjz # SxTRbcwSq+6aPjQIn0RWp8Hp1HkdNjegB98dkyqRLlVaugHZWPYDXDQTgVziQlX8 # dU8YrlvTOtDWwsNP6awWnW6/IjKuJjGR0wT3QKwi8JAZ0YV3egwEKoQRUAyHtnn2 # FkSMYgmJcF0ai1aIJFAx+3PIzCfS49lKXA0t303DtY3hRR9JKGMwaV2do9Wm2irt # o7T1lKKN7R7R8Q3U4OsatYMYm7KYL07NEDiQCPloGvCo27ezkAWCKXAw1mRUkxKF # jKwJPcnOUq21Jp6tpjsR8ifSw70jBSEWQSGqhXnDhZhx2C2/Qqkg2I8DagLiPger # kYxbQ13LTG0R25YHa1r3UmzuD+HpZOM8XoLJc5yun/1UrwyR9ghHrOoxkSnRT2Ks # QFn//xQ2SzUnGBNzNSMfTk8vzludxSWfFnOjkviF6E2Elnw3p8f/kOQRAft5dMBY # ftgoy2yLone3HpKfjuOriicIzg== # =0GLo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 Apr 2022 06:47:55 AM PDT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] * tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu: (30 commits) qga: use fixed-length and GDateTime for log timestamp tests/fuzz: fix warning qga: remove need for QEMU atomic.h util: replace qemu_get_local_state_pathname() util: use qemu_create() in qemu_write_pidfile() util: use qemu_write_full() in qemu_write_pidfile() util: simplify write in signal handler qtest: simplify socket_send() qga: move qga_get_host_name() Move error_printf_unless_qmp() with monitor unit tests: run-time skip test-qga if TSAN is enabled compiler.h: add QEMU_SANITIZE_{ADDRESS,THREAD} tests: remove block/qdict checks from check-qobject.c include: move qdict_{crumple,flatten} declarations include: add qemu/keyval.h include: move qemu_fdatasync() to osdep include: move qemu_msync() to osdep compiler.h: replace QEMU_NORETURN with G_NORETURN osdep.h: move qemu_build_not_reached() doc/style: CLang -> Clang ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
140 lines
4.9 KiB
C
140 lines
4.9 KiB
C
/*
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* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
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*
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* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
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* All rights reserved.
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*
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* Evgeny Voevodin <e.voevodin@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/exynos4210_gic.h"
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#include "hw/arm/exynos4210.h"
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#include "qom/object.h"
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#define EXYNOS4210_GIC_NIRQ 160
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#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
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#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
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#define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000
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#define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \
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((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
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#define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \
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((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
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#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
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#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
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static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
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{
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Exynos4210GicState *s = (Exynos4210GicState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
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}
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static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
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{
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Object *obj = OBJECT(dev);
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Exynos4210GicState *s = EXYNOS4210_GIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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SysBusDevice *gicbusdev;
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uint32_t n = s->num_cpu;
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uint32_t i;
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s->gic = qdev_new("arm_gic");
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qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ);
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gicbusdev = SYS_BUS_DEVICE(s->gic);
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sysbus_realize_and_unref(gicbusdev, &error_fatal);
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/* Pass through outbound IRQ lines from the GIC */
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sysbus_pass_irq(sbd, gicbusdev);
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(dev, exynos4210_gic_set_irq,
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EXYNOS4210_GIC_NIRQ - 32);
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memory_region_init(&s->cpu_container, obj, "exynos4210-cpu-container",
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EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
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memory_region_init(&s->dist_container, obj, "exynos4210-dist-container",
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EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
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/*
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* This clues in gcc that our on-stack buffers do, in fact have
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* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
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* doesn't figure this out, otherwise and gives spurious warnings.
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*/
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assert(n <= EXYNOS4210_GIC_NCPUS);
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for (i = 0; i < n; i++) {
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g_autofree char *cpu_alias_name = g_strdup_printf("exynos4210-gic-alias_cpu%u", i);
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g_autofree char *dist_alias_name = g_strdup_printf("exynos4210-gic-alias_dist%u", i);
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/* Map CPU interface per SMP Core */
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memory_region_init_alias(&s->cpu_alias[i], obj,
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cpu_alias_name,
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sysbus_mmio_get_region(gicbusdev, 1),
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0,
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EXYNOS4210_GIC_CPU_REGION_SIZE);
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memory_region_add_subregion(&s->cpu_container,
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EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);
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/* Map Distributor per SMP Core */
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memory_region_init_alias(&s->dist_alias[i], obj,
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dist_alias_name,
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sysbus_mmio_get_region(gicbusdev, 0),
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0,
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EXYNOS4210_GIC_DIST_REGION_SIZE);
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memory_region_add_subregion(&s->dist_container,
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EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
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}
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sysbus_init_mmio(sbd, &s->cpu_container);
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sysbus_init_mmio(sbd, &s->dist_container);
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}
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static Property exynos4210_gic_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, exynos4210_gic_properties);
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dc->realize = exynos4210_gic_realize;
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}
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static const TypeInfo exynos4210_gic_info = {
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.name = TYPE_EXYNOS4210_GIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Exynos4210GicState),
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.class_init = exynos4210_gic_class_init,
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};
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static void exynos4210_gic_register_types(void)
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{
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type_register_static(&exynos4210_gic_info);
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}
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type_init(exynos4210_gic_register_types)
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