Michael Clark 1d1ee55274 RISC-V: Make mtvec/stvec ignore vectored traps ... Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>		2018-05-06 10:39:38 +12:00
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cpu_bits.h
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Update E and I extension order	2018-05-06 10:39:38 +12:00
cpu.h	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	2018-05-06 10:39:38 +12:00
fpu_helper.c	RISC-V FPU Support	2018-03-07 08:30:28 +13:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	RISC-V: Clear mtval/stval on exceptions without info	2018-05-06 10:39:38 +12:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: Make mtvec/stvec ignore vectored traps	2018-05-06 10:39:38 +12:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Add mcycle/minstret support for -icount auto	2018-05-06 10:39:38 +12:00