Bastian Koppelmann 1bd3e2fc3d target-tricore: Fix psw_read() clearing too many bits ... psw_read() ought to sync the PSW value with the cached status bits (C,V,SV,AV,SAV). For this the bits are cleared in the PSW before they are written from the cached bits. The clear mask is too big and clears two additional bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1458547383-23102-4-git-send-email-kbastian@mail.uni-paderborn.de>		2016-03-23 09:22:48 +01:00
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cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	tricore: Clean up includes	2016-01-29 15:07:25 +00:00
cpu.h	target-tricore: Add trap handling & SOVF/OVF traps	2016-02-25 12:54:42 +01:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	target-tricore: Fix psw_read() clearing too many bits	2016-03-23 09:22:48 +01:00
helper.h	target-tricore: Add trap handling & SOVF/OVF traps	2016-02-25 12:54:42 +01:00
Makefile.objs	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
op_helper.c	target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit	2016-03-23 09:22:48 +01:00
translate.c	target-tricore: add missing break in insn decode switch stmt	2016-03-23 09:22:48 +01:00
tricore-defs.h	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
tricore-opcodes.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00