Andrew Jeffery 0c69996e22 hw/intc: Add (new) ASPEED VIC device model ... Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with enough functionality to boot an aspeed_defconfig Linux kernel. The model implements the 'new' (revised) register set: While the hardware exposes both the new and legacy register sets, accesses to the model's legacy register set will not be serviced (however the access will be logged). [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2016-03-16 17:42:18 +00:00
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allwinner-a10-pic.h	hw/intc: add allwinner A10 interrupt controller	2013-12-17 20:12:51 +00:00
arm_gic_common.h	arm_gic_kvm: Disable live migration if not supported	2015-10-27 12:00:50 +00:00
arm_gic.h
arm_gicv3_common.h	hw/intc: Implement GIC-500 base class	2015-09-24 01:29:36 +01:00
aspeed_vic.h	hw/intc: Add (new) ASPEED VIC device model	2016-03-16 17:42:18 +00:00
bcm2835_ic.h	bcm2835_ic: add bcm2835 interrupt controller	2016-02-03 15:00:44 +00:00
bcm2836_control.h	bcm2836_control: add bcm2836 ARM control logic	2016-02-03 15:00:45 +00:00
imx_avic.h	i.MX: Split AVIC emulator in a header file and a source file	2015-08-13 11:26:19 +01:00
realview_gic.h	realview_gic: Prepare for QOM embedding	2013-11-05 17:47:30 +01:00