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091a35165f
qemu/target/openrisc
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Richard Henderson 091a35165f target/openrisc: Fix lf.ftoi.s 
The specification of this insn is round-to-zero.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-04 12:51:56 -07:00
..
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/openrisc: Add VR2 and AVR special processor registers 2019-09-04 12:51:19 -07:00
cpu.h target/openrisc: Add VR2 and AVR special processor registers 2019-09-04 12:51:19 -07:00
disas.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
exception_helper.c target/openrisc: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
exception.c target/openrisc: Fix LGPL information in the file headers 2019-05-08 17:45:54 +02:00
exception.h Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
fpu_helper.c target/openrisc: Fix lf.ftoi.s 2019-09-04 12:51:56 -07:00
gdbstub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
helper.h target/openrisc: Fix LGPL version number 2019-01-30 11:01:36 +01:00
insns.decode target/openrisc: Fix LGPL information in the file headers 2019-05-08 17:45:54 +02:00
interrupt_helper.c target/openrisc: Fix LGPL version number 2019-01-30 11:01:36 +01:00
interrupt.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
machine.c Include hw/boards.h a bit less 2019-08-16 13:31:53 +02:00
Makefile.objs target/openrisc: Merge mmu_helper.c into mmu.c 2018-07-03 00:05:28 +09:00
mmu.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
sys_helper.c target/openrisc: Add VR2 and AVR special processor registers 2019-09-04 12:51:19 -07:00
translate.c target/openrisc: Cache R0 in DisasContext 2019-09-04 12:48:12 -07:00