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066e9b2710
Hot-add CPU event will be distributed to acpi_piix4 and rtc_cmos. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* QEMU CPU model
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qom/cpu.h"
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#include "qemu-common.h"
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#include "sysemu/kvm.h"
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#include "qemu/notify.h"
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#include "sysemu/sysemu.h"
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/* CPU hot-plug notifiers */
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static NotifierList cpu_added_notifiers =
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NOTIFIER_LIST_INITIALIZER(cpu_add_notifiers);
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void qemu_register_cpu_added_notifier(Notifier *notifier)
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{
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notifier_list_add(&cpu_added_notifiers, notifier);
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}
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void cpu_reset_interrupt(CPUState *cpu, int mask)
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{
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cpu->interrupt_request &= ~mask;
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}
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void cpu_reset(CPUState *cpu)
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{
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CPUClass *klass = CPU_GET_CLASS(cpu);
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if (klass->reset != NULL) {
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(*klass->reset)(cpu);
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}
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}
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static void cpu_common_reset(CPUState *cpu)
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{
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cpu->exit_request = 0;
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cpu->interrupt_request = 0;
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cpu->current_tb = NULL;
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cpu->halted = 0;
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}
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ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
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{
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CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
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return cc->class_by_name(cpu_model);
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}
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static ObjectClass *cpu_common_class_by_name(const char *cpu_model)
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{
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return NULL;
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}
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static void cpu_common_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cpu = CPU(dev);
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if (dev->hotplugged) {
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cpu_synchronize_post_init(cpu);
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notifier_list_notify(&cpu_added_notifiers, dev);
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cpu_resume(cpu);
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}
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}
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static void cpu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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CPUClass *k = CPU_CLASS(klass);
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k->class_by_name = cpu_common_class_by_name;
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k->reset = cpu_common_reset;
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dc->realize = cpu_common_realizefn;
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dc->no_user = 1;
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}
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static const TypeInfo cpu_type_info = {
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.name = TYPE_CPU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CPUState),
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.abstract = true,
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.class_size = sizeof(CPUClass),
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.class_init = cpu_class_init,
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};
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static void cpu_register_types(void)
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{
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type_register_static(&cpu_type_info);
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}
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type_init(cpu_register_types)
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