Emilio G. Cota 0114db1c82 target/riscv: convert to DisasContextBase ... Notes: - Did not convert {num,max}_insns, since the corresponding code will go away in the next patch. - ctx->pc becomes ctx->base.pc_next, and ctx->next_pc becomes ctx->pc_succ_insn. While at it, convert the remaining tb->cflags readers to tb_cflags(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Michael Clark <mjc@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2018-05-09 10:12:21 -07:00
..
cpu_bits.h
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Update E and I extension order	2018-05-06 10:39:38 +12:00
cpu.h	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	2018-05-06 10:39:38 +12:00
fpu_helper.c	RISC-V FPU Support	2018-03-07 08:30:28 +13:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	RISC-V: Clear mtval/stval on exceptions without info	2018-05-06 10:39:38 +12:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: No traps on writes to misa,minstret,mcycle	2018-05-06 10:39:38 +12:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: convert to DisasContextBase	2018-05-09 10:12:21 -07:00