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00e1754ff1
qemu/target-tricore
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Bastian Koppelmann 00e1754ff1 target-tricore: fix RRPW_DEXTR using wrong reg 
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24 09:45:28 +01:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Several translator and cpu model fixes 2015-01-26 19:56:45 +00:00
cpu.h target-tricore: Add instructions of SYS opcode format 2015-03-16 15:53:08 +00:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of SYS opcode format 2015-03-16 15:53:08 +00:00
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
op_helper.c target-tricore: Fix two helper functions (clang warnings) 2015-03-24 09:45:28 +01:00
translate.c target-tricore: fix RRPW_DEXTR using wrong reg 2015-03-24 09:45:28 +01:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode 2015-03-16 15:44:48 +00:00