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7cac7aa704
The call to xgetbv() is passing the ecx value for cpuid function 0xD, index 0. The xgetbv call thus returns false (OSXSAVE is bit 27, which is well out of the range of CPUID[0xD,0].ECX) and eax is not modified. While fixing it, cache the whole computation of supported XCR0 bits since it will be used for more than just CPUID leaf 0xD. Furthermore, unsupported subleafs of CPUID 0xD (including all those corresponding to zero bits in host's XCR0) must be hidden; if OSXSAVE is not set at all, the whole of CPUID leaf 0xD plus the XSAVE bit must be hidden. Finally, unconditionally drop XSTATE_BNDREGS_MASK and XSTATE_BNDCSR_MASK; real hardware will only show them if the MPX bit is set in CPUID; this is never the case for hvf_get_supported_cpuid() because QEMU's Hypervisor.framework support does not handle the VMX fields related to MPX (even in the unlikely possibility that the host has MPX enabled). So hide those bits in the new cache_host_xcr0(). Cc: Phil Dennis-Jordan <lists@philjordan.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
103 lines
3.5 KiB
C
103 lines
3.5 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Host specific cpu identification for x86.
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*/
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#include "qemu/osdep.h"
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#include "host/cpuinfo.h"
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#ifdef CONFIG_CPUID_H
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# include "qemu/cpuid.h"
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#endif
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unsigned cpuinfo;
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/* Called both as constructor and (possibly) via other constructors. */
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unsigned __attribute__((constructor)) cpuinfo_init(void)
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{
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unsigned info = cpuinfo;
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if (info) {
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return info;
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}
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#ifdef CONFIG_CPUID_H
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unsigned max, a, b, c, d, b7 = 0, c7 = 0;
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max = __get_cpuid_max(0, 0);
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if (max >= 7) {
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__cpuid_count(7, 0, a, b7, c7, d);
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info |= (b7 & bit_BMI ? CPUINFO_BMI1 : 0);
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info |= (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0);
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}
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if (max >= 1) {
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__cpuid(1, a, b, c, d);
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info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
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info |= (c & bit_OSXSAVE ? CPUINFO_OSXSAVE : 0);
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info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
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info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
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info |= (c & bit_PCLMUL ? CPUINFO_PCLMUL : 0);
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/* Our AES support requires PSHUFB as well. */
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info |= ((c & bit_AES) && (c & bit_SSSE3) ? CPUINFO_AES : 0);
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/* For AVX features, we must check available and usable. */
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if ((c & bit_AVX) && (c & bit_OSXSAVE)) {
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unsigned bv = xgetbv_low(0);
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if ((bv & 6) == 6) {
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info |= CPUINFO_AVX1;
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info |= (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0);
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if ((bv & 0xe0) == 0xe0) {
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info |= (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0);
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info |= (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0);
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info |= (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0);
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info |= (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0);
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info |= (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 : 0);
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}
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/*
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* The Intel SDM has added:
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* Processors that enumerate support for Intel® AVX
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* (by setting the feature flag CPUID.01H:ECX.AVX[bit 28])
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* guarantee that the 16-byte memory operations performed
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* by the following instructions will always be carried
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* out atomically:
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* - MOVAPD, MOVAPS, and MOVDQA.
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* - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128.
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* - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded
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* with EVEX.128 and k0 (masking disabled).
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* Note that these instructions require the linear addresses
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* of their memory operands to be 16-byte aligned.
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*
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* AMD has provided an even stronger guarantee that processors
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* with AVX provide 16-byte atomicity for all cacheable,
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* naturally aligned single loads and stores, e.g. MOVDQU.
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*
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* See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
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*/
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__cpuid(0, a, b, c, d);
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if (c == signature_INTEL_ecx) {
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info |= CPUINFO_ATOMIC_VMOVDQA;
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} else if (c == signature_AMD_ecx) {
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info |= CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOVDQU;
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}
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}
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}
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}
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max = __get_cpuid_max(0x8000000, 0);
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if (max >= 1) {
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__cpuid(0x80000001, a, b, c, d);
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info |= (c & bit_LZCNT ? CPUINFO_LZCNT : 0);
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}
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#endif
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info |= CPUINFO_ALWAYS;
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cpuinfo = info;
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return info;
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}
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