Commit Graph

312 Commits

Author SHA1 Message Date
Nathan Froyd
bf4120adaa target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes and
tweak a few places to use them.  Add enums for various invocations of
FOP and tweak gen_farith and its lone caller accordingly.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:50 +02:00
Nathan Froyd
26ebe46848 target-mips: break out [ls][wd]c1 and rdhwr insn generation
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-08 19:15:08 +02:00
Richard Henderson
564856bb97 target-mips: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-05 12:20:05 +02:00
Stefan Weil
2a5612e6a3 target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function to
allow parameter checking by gcc some compiler warnings
remained unfixed.

These warnings are fixed here.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09 21:53:23 +02:00
Stefan Weil
a7200c9f98 target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:46:57 +02:00
Paolo Bonzini
1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Aurelien Jarno
deb4203dc9 target-mips: use newer logical ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-04 17:42:03 +01:00
Aurelien Jarno
e68dd28fd7 target-mips: use setcond when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:16:56 +01:00
Nathan Froyd
3399e30f56 target-mips: fix ROTR and DROTR by zero
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:25 +01:00
Nathan Froyd
c2c65dab45 target-mips: fix CpU exception for coprocessor 0
When we signal a CpU exception for coprocessor 0, we should indicate
that it's for coprocessor 0 instead of coprocessor 1.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Aurelien Jarno
6462bfcded target-mips: remove useless sign extension
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Nathan Froyd
91a7593526 target-mips: fix user-mode emulation startup
Running programs with the MIPS user-mode emulator fails during dynamic
loading, as floating-point instructions are not enabled in in
env->hflags.  Move the code for doing so from fpu_init to cpu_reset so
the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset
setting env->hflags to MIPS_HFLAG_UM.

The same end can be achieved by swapping the ordering of fpu_init and
cpu_reset in cpu_mips_init, but it seemed better to consolidate the
CONFIG_USER_ONLY code into a single location.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 21:01:33 +01:00
Nathan Froyd
9da53be7ea target-mips: add copyright notice for mips16 work
Also cross off mips16 ASE in TODO.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
364d48314a target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.
The only changes to shared code are in handle_delay_slot.  We need to
flip ISAMode when doing a jump-and-exchange.  We also need to set
ISAMode the low bit of the target address for jump-to-register.

Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT,
make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want
basic information about a branch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
6ea219d019 target-mips: add enums for MIPS16 opcodes
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd
c960206137 target-mips: split out delay slot handling
Move delay slot handling to common code whose invocation can be
controlled from gen_intermediate_code_internal.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
662d748516 target-mips: add gen_base_offset_addr
This is a common pattern in existing code.  We'll also use it to
implement the mips16 SAVE/RESTORE instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
7dca4ad050 target-mips: make gen_compute_branch 16/32-bit-aware
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd
ea63e2c358 target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're not
examining the opcode inside gen_shift_{imm,}.  So move ROTR and ROTRV
and do the special-case handling of SRL and SRLV inside decode_opc.
Likewise for their 64-bit counterparts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Aurelien Jarno
e7139c440c target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:18:28 +01:00
Aurelien Jarno
2a6e32dd46 target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
Aurelien Jarno
5499b6ffac target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:12:13 +01:00
Aurelien Jarno
31e3104fdb target-mips: fix indentation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 13:10:00 +01:00
Blue Swirl
51cc2e783a mips: fix cpu_reset memory leak
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 02:25:52 +01:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Aurelien Jarno
941694d09a target-mips: make sure constants are in the second argument
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 23:12:51 +02:00
Stefan Weil
a0d700e43b mips: Fix spelling in comment
inofficial -> unofficial

Thanks to Blue Swirl.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30 19:07:15 +00:00
Aurelien Jarno
618b0fe9ab target-mips: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-28 13:03:30 +02:00
Aurelien Jarno
d42320c26a target-mips: remove MAX_OP_PER_INSTR workaround
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed
the target-mips specific workaround.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-23 09:25:03 +02:00
Nathan Froyd
7b270ef2a3 target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because the
generation of EXCP_DEBUG happened after the generation of the code to
exit the current TB.  That is, given the code:

    bne v0,v1,target
    nop
    ...
  target:
    addu v0,v0,v1
  1:

when you single-stepped through the NOP, execution wouldn't actually
halt until you reached the label `1'.

This patch corrects that and also changes single-stepping so that a
branch and its delay slot are executed as one instruction for the
purposes of single-stepping.  This behavior is comparable to what other
MIPS tools (e.g. MIPSsim with MDI) do.  GDB avoids placing breakpoints
in branch delay slots, so this change doesn't break anything on the GDB
side.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-14 19:34:12 +02:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Nathan Froyd
fa31af0e63 target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code.  However,
get_fp_bit returns the bit number of the condition code, not a
bitmask.  (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)

Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-25 18:05:27 +02:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Aurelien Jarno
344b983d9b target-mips: remove useless code in gen_st_cond()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12 15:09:01 +02:00
Paul Brook
feeb3b6a7a Fix MIPS SC
Fix botched merge of op_ldst_sc calls to match actual implementation.
Thanks to Aurelien Jarno for diagnosing this.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-12 13:11:25 +01:00
Paul Brook
590bc601d8 MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 17:45:17 +01:00
Nathan Froyd
98070ce00f target-mips: fix MADD and MSUB/MSUBU instructions
MADD was not correctly writing to HI.

MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-03 03:28:20 +02:00
Blue Swirl
001faf3269 Replace gcc variadic macro extension with C99 version
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13 17:53:17 +00:00
Aurelien Jarno
6bb72b184d target-mips: proper sign extension for 'SUBU rd, zero, rt'
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04 10:05:21 +02:00
Aurelien Jarno
88cbb9804b target-mips: fix comments about SUB/DSUB
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04 10:05:15 +02:00
aliguori
0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:41 +00:00
pbrook
df357f0e62 Enable access to SYNCI_Step register in usermode emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7191 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-20 23:55:57 +00:00
aurel32
8c0ab41f4a Revert "target-mips: fix call to check_*() functions"
This reverts commit r7127, r7132 is a better fix for that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7133 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17 13:17:26 +00:00
aurel32
aefbc83e95 target-mips: simplify exception generation
There is no need to exit the tb after a call to helper_raise_exception
as it already calls cpu_loop_exit().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7132 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17 13:11:42 +00:00
aurel32
a6035857db target-mips: fix revision r7126
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7128 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 12:57:50 +00:00
aurel32
007ac6faed target-mips: fix call to check_*() functions
check_*() functions may in fine call generate_exception(), which ends
by a call to tcg_gen_exit_tb(). As a consequence, we have to make sure
that no TCG temp variables are crossing a check_*() function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7127 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:19 +00:00
aurel32
585c88d5af target-mips: optimize gen_flt3_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:11 +00:00
aurel32
c407df8156 target-mips: optimize gen_flt_ldst()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7125 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 11:51:03 +00:00
pbrook
8e0f950d89 Stop translation after a syscall instruciton.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7124 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16 10:56:43 +00:00