Commit Graph

22430 Commits

Author SHA1 Message Date
Richard Henderson
97ea285917 target-sparc: Conversion to gen_*_gpr, part 1
Only handle the easy cases directly within disas_sparc_insn.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:06 +00:00
Richard Henderson
8802361689 target-sparc: Add gen_load/store/dest_gpr
Infrastructure to be used to clean up handling of temporaries.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:56:05 +00:00
Richard Henderson
74d590c8e9 exec: Make MIN_CODE_GEN_BUFFER_SIZE private to exec.c
It is used nowhere else, and the corresponding MAX_CODE_GEN_BUFFER_SIZE
also lives there.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:54:04 +00:00
Richard Henderson
4438c8a946 exec: Allocate code_gen_prologue from code_gen_buffer
We had a hack for arm and sparc, allocating code_gen_prologue to a
special section.  Which, honestly does no good under certain cases.
We've already got limits on code_gen_buffer_size to ensure that all
TBs can use direct branches between themselves; reuse this limit to
ensure the prologue is also reachable.

As a bonus, we get to avoid marking a page of the main executable's
data segment as executable.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:54:04 +00:00
Richard Henderson
405def1846 exec: Do not use absolute address hints for code_gen_buffer with -fpie
The hard-coded addresses inside alloc_code_gen_buffer only make sense
if we're building an executable that will actually run at the address
we've put into the linker scripts.

When we're building with -fpie, the executable will run at some
random location chosen by the kernel.  We get better placement for
the code_gen_buffer if we allow the kernel to place the memory,
as it will tend to to place it near the executable, based on the
PROT_EXEC bit.

Since code_gen_prologue is always inside the executable, this effect
is easily seen at the end of most TB, with the exit_tb opcode, and
with any calls to helper functions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:54:04 +00:00
Richard Henderson
3d85a72fd8 exec: Don't make DEFAULT_CODE_GEN_BUFFER_SIZE too large
For ARM we cap the buffer size to 16MB.  Do not allocate 32MB in that case.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:54:04 +00:00
Richard Henderson
f1bc0bcc9d exec: Split up and tidy code_gen_buffer
It now consists of:

A macro definition of MAX_CODE_GEN_BUFFER_SIZE with host-specific values,

A function size_code_gen_buffer that applies most of the reasoning for
choosing a buffer size,

Three variations of a function alloc_code_gen_buffer that contain all
of the logic for allocating executable memory via a given allocation
mechanism.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:54:04 +00:00
Eduardo Habkost
5f072e1f30 create struct for machine initialization arguments
This should help us to:
- More easily add or remove machine initialization arguments without
  having to change every single machine init function;
- More easily make mechanical changes involving the machine init
  functions in the future;
- Let machine initialization forward the init arguments to other
  functions more easily.

This change was half-mechanical process: first the struct was added with
the local ram_size, boot_device, kernel_*, initrd_*, and cpu_model local
variable initialization to all functions. Then the compiler helped me
locate the local variables that are unused, so they could be removed.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:53:28 +00:00
Gerd Hoffmann
a96d8bea8e vga: remove CONFIG_BOCHS_VBE
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:52:54 +00:00
Gerd Hoffmann
cc22824860 vga: add specs for standard vga
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:52:54 +00:00
Gerd Hoffmann
803ff052b6 vga: add mmio bar to standard vga
This patch adds a mmio bar to the qemu standard vga which allows to
access the standard vga registers and bochs dispi interface registers
via mmio.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:52:54 +00:00
Gerd Hoffmann
0d0302e203 vga: fix indention
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-20 07:52:54 +00:00
Catalin Patulea
f62cb1b6dd tests/tcg: fix build
This broke when the tests were moved from tests/ to tests/tcg/.

On x86_64 host/i386-linux-user non-kvm guest, test-i386 and test-mmap are broken, but at least they build.

To build/run the tests:
$ cd $BUILD_PATH/tests/tcg
$ SRC_PATH=path/to/qemu make <target>

Signed-off-by: Catalin Patulea <catalinp@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:40:21 +02:00
Mike Frysinger
7748b8cb1d allow make {dist, }clean work w/out configure
There's no reason to require configure to run before running a clean
target, so check MAKECMDGOALS before.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:39:36 +02:00
Michael Roth
42a1592845 tci: fix build breakage for target-sparc
commit c28ae41 introduced GETPC() usage for sparc, which is currently
not defined when building with --enable-tcg-interpreter. Add sparc to
the list of targets we selectively define GETPC() for.

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:38:29 +02:00
Stefan Hajnoczi
1cd0f8ce73 MAINTAINERS: Update email address for Stefan Hajnoczi
Switch to my new work email address from which I am contributing.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:37:43 +02:00
Jan Kiszka
38f419f352 configure: Fix CONFIG_QEMU_HELPERDIR generation
We need to evaluate $libexecdir in configure, otherwise we literally end
up with "${prefix}/libexec" instead of the absolute path as
CONFIG_QEMU_HELPERDIR.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:35:33 +02:00
Peter Maydell
585f60368f qemu-options.hx: Change from recommending '?' to 'help'
Update the -help output and documentation so that it recommends
'help' rather than '?' for the various "list valid values for this
option" cases. '?' is deprecated (as it can fail confusingly if
not quoted), so it's better to steer users towards 'help'. ('?'
still works, for backwards compatibility.)

This is the -help option part of the change otherwise done in
commit c8057f9, since we are now past release 1.2 and free to
change our help text without worrying about breaking libvirt.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:29:54 +02:00
Aurelien Jarno
41a05a4576 Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu
* 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu:
  linux-user: register align p{read, write}64
  linux-user: ppc: mark as long long aligned
  tcg: Remove TCG_TARGET_HAS_GUEST_BASE define
  configure: Remove unnecessary host_guest_base code
  linux-user: If loading fails, print error as string, not number
  linux-user: Fix siginfo handling
  alpha-linux-user: Fix sigaltstack structure definition
  linux-user: Implement gethostname
  linux-user: Perform more checks on iovec lists
  linux-user: fix multi-threaded /proc/self/maps
  linux-user: fix statfs
2012-10-19 20:28:22 +02:00
Aurelien Jarno
3e50da6525 Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
* 'trivial-patches' of git://github.com/stefanha/qemu:
  ui/vnc-jobs.c: Fix minor typos in comments
  net/tap-win32: Fix compiler warning caused by missing include statement
  configure: Remove unused parameters from main function
  target-arm/neon_helper: Remove obsolete FIXME comment
  targphys.h: Don't define target_phys_addr_t for user-mode emulators
  ui/vnc: Only report/use TIGHT_PNG encoding if enabled.
2012-10-19 20:18:44 +02:00
Edgar E. Iglesias
d7dce49476 microblaze: Update PC before simulating syscall
Fixes a clone() emulation bug were the new thread starts
at the point of the syscall and thus clones in a loop.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-10-19 13:24:12 +02:00
Edgar E. Iglesias
a5b3bdcba8 microblaze: Support setting of TLS ptr
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-10-19 13:24:12 +02:00
Peter Maydell
11f6697861 ui/vnc-jobs.c: Fix minor typos in comments
Fix some minor typos/grammar errors in comments.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:42:01 +02:00
Stefan Weil
08778b3983 net/tap-win32: Fix compiler warning caused by missing include statement
The include file for net_init_tap was missing:

net/tap-win32.c:703:
 warning: no previous prototype for ‘net_init_tap’

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:39:35 +02:00
Stefan Weil
abab1a0f32 configure: Remove unused parameters from main function
This modification is required if compiler option -Wunused-parameter is activated.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:38:53 +02:00
Peter Maydell
02c7ac0c0f target-arm/neon_helper: Remove obsolete FIXME comment
Commit 33ebc29 fixed the bugs in the implementation of VQRSHL,
but forgot to remove the FIXME comment...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:32:24 +02:00
Peter Maydell
301592ea6f targphys.h: Don't define target_phys_addr_t for user-mode emulators
Commit 4be403c accidentally defined the target_phys_addr_t type when
building user-mode emulators. Since the type doesn't really make
any sense except for system emulators, avoid defining it when building
in user mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:31:51 +02:00
Joel Martin
fe3e7f2dc0 ui/vnc: Only report/use TIGHT_PNG encoding if enabled.
If TIGHT_PNG is not enabled by the --enable-vnc-png configure flag
then do not report to the client that it is supported.

Also, since TIGHT_PNG is the same as the TIGHT encoding but with the
filter/copy replaced with PNG data, adding it to the supported
encodings list when it is disabled will cause the TIGHT encoding to be
used even though the client requested TIGHT_PNG.

Signed-off-by: Joel Martin <github@martintribe.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-19 10:27:37 +02:00
Peter Crosthwaite
b6348f29d0 target-arm/translate: Fix RRX operands
Instructions that both use the RRX second operand and update CS were
incorrect, as the Carry flag was updated too early. An example of such an
instruction would be:

ands r12,r13,RRX

Ands, because of the "s" flag will update the carry flag. But the RRX second
operand rotates through the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Vinesh Peringat <vineshp@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 19:56:46 +02:00
Richard Henderson
1414968a6a tcg: Optimize mulu2
Like add2, do operand ordering, constant folding, and dead operand
elimination.  The latter happens about 15% of all mulu2 during an
x86_64 bios boot.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:51:39 +02:00
Richard Henderson
1305c451e6 tcg: Optimize half-dead add2/sub2
When x86_64 guest is not in 64-bit mode, the high-part of the 64-bit
add is dead.  When the host is 32-bit, we can simplify to 32-bit
arithmetic.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:51:37 +02:00
Richard Henderson
212c328d61 tcg: Constant fold add2 and sub2
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:51:37 +02:00
Richard Henderson
6c4382f8f4 tcg: Do constant folding on double-word comparisons
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:51:35 +02:00
Richard Henderson
9519da7e39 tcg: Split out subroutines from do_constant_folding_cond
We can re-use these for implementing double-word folding.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:51:32 +02:00
Richard Henderson
bc1473eff4 tcg: Optimize double-word comparisons against zero
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:32:29 +02:00
Richard Henderson
6e14e91b66 tcg: Use common code when failing to optimize
This saves a whole lot of repetitive code sequences.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:32:01 +02:00
Richard Henderson
0bfcb86538 tcg: Swap commutative double-word comparisons
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:31:57 +02:00
Richard Henderson
1e484e61e2 tcg: Canonicalize add2 operand ordering
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:31:53 +02:00
Richard Henderson
24c9ae4eba tcg: Split out swap_commutative as a subroutine
Reduces code duplication and prefers

  movcond d, c1, c2, const, s
to
  movcond d, c1, c2, s, const

It also prefers

  add r, r, c
over
  add r, c, r

when both inputs are known constants.  This doesn't matter for true add, as
we will fully constant fold that.  But it matters for a follow-on patch using
this routine for add2 which may not be fully foldable.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 17:30:40 +02:00
Andreas Färber
6f4d6b0908 target-mips: Pass MIPSCPU to mips_vpe_sleep()
Needed for moving halted field to CPUState.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
c6679e9038 target-mips: Pass MIPSCPU to mips_tc_sleep()
Needed for changing mips_vpe_sleep() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
b35d77d73c target-mips: Pass MIPSCPU to mips_vpe_is_wfi()
Needed for moving halted field to CPUState.
The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.

Also change return type to bool while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:11 +02:00
Andreas Färber
135dd63a19 target-mips: Pass MIPSCPU to mips_tc_wake()
Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:10 +02:00
Andreas Färber
81bad50ec4 target-mips: Clean up other_cpu in helper_{d,e}vpe()
Free the variable name "other_cpu" for later use for MIPSCPU.

Fix off-by-one indentation while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:32:10 +02:00
Richard Henderson
c7d4475a70 tcg-ia64: Implement deposit
Note that in the general reg=reg,reg case we're restricted
to 16-bit insertions.  This makes it easy to allow "any"
constant as input, as post-truncation it will fit into the
constant load insn for which we have room in the bundle.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
63975ea7df tcg/ia64: slightly optimize TLB access code
It is possible to slightly optimize the TLB access code, by replacing
the movi + and instructions by a deposit instruction.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
2174d1e1ff tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops
Remove suboptimal register shifting in qemu_ld/st ops, introduced at the
CONFIG_TCG_PASS_AREG0 time.

As mem_idx is now loaded in register R58/R59 for the slow path, we have
to make sure to do it last, to not add additional register constraints.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:43 +02:00
Aurelien Jarno
b90cf71692 tcg/ia64: implement movcond_i32/64
Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:42 +02:00
Blue Swirl
da897bf5ae tcg/ia64: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:26:42 +02:00
Peter Maydell
4a1d241e3c tcg/arm: Implement movcond_i32
Implement movcond_i32 for ARM, as the sequence
  mov dst, v2   (implicitly done by the tcg common code)
  cmp c1, c2
  movCC dst, v1

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-17 01:22:49 +02:00