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target-sparc: move common cpu initialisation routines to sparc64.c
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Artyom Tarasenko
parent
a0e893039c
commit
fff54d2269
@ -1 +1,2 @@
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obj-y += sparc64.o
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obj-y += sun4u.o
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378
hw/sparc64/sparc64.c
Normal file
378
hw/sparc64/sparc64.c
Normal file
@ -0,0 +1,378 @@
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/*
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* QEMU Sun4u/Sun4v System Emulator common routines
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/char/serial.h"
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#include "hw/sparc/sparc64.h"
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#include "qemu/timer.h"
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//#define DEBUG_IRQ
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//#define DEBUG_TIMER
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#ifdef DEBUG_IRQ
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#define CPUIRQ_DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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#define TICK_MAX 0x7fffffffffffffffULL
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = CPU(sparc_env_get_cpu(env));
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/* The bit corresponding to psrpil is (1<< psrpil), the next bit
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is (2 << psrpil). */
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if (pil < (2 << env->psrpil)) {
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n",
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env->tl, cpu_tsptr(env)->tt, new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUSPARCState *env = &cpu->env;
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cs->halted = 0;
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cpu_check_irqs(env);
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qemu_cpu_kick(cs);
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}
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void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUState *cs;
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if (level) {
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if (!(env->ivec_status & 0x20)) {
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CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
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cs = CPU(cpu);
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cs->halted = 0;
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env->interrupt_index = TT_IVEC;
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env->ivec_status |= 0x20;
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env->ivec_data[0] = (0x1f << 6) | irq;
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env->ivec_data[1] = 0;
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env->ivec_data[2] = 0;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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} else {
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if (env->ivec_status & 0x20) {
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CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
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cs = CPU(cpu);
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env->ivec_status &= ~0x20;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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typedef struct ResetData {
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SPARCCPU *cpu;
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uint64_t prom_addr;
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} ResetData;
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static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
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QEMUBHFunc *cb, uint32_t frequency,
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uint64_t disabled_mask, uint64_t npt_mask)
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{
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CPUTimer *timer = g_malloc0(sizeof(CPUTimer));
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timer->name = name;
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timer->frequency = frequency;
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timer->disabled_mask = disabled_mask;
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timer->npt_mask = npt_mask;
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timer->disabled = 1;
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timer->npt = 1;
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timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
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return timer;
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}
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static void cpu_timer_reset(CPUTimer *timer)
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{
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timer->disabled = 1;
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timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer_del(timer->qtimer);
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}
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUSPARCState *env = &s->cpu->env;
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static unsigned int nr_resets;
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cpu_reset(CPU(s->cpu));
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cpu_timer_reset(env->tick);
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cpu_timer_reset(env->stick);
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cpu_timer_reset(env->hstick);
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env->gregs[1] = 0; /* Memory start */
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env->gregs[2] = ram_size; /* Memory size */
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env->gregs[3] = 0; /* Machine description XXX */
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if (nr_resets++ == 0) {
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/* Power on reset */
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env->pc = s->prom_addr + 0x20ULL;
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} else {
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env->pc = s->prom_addr + 0x40ULL;
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}
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env->npc = env->pc + 4;
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}
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static void tick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->tick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("tick: fire\n");
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}
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env->softint |= SOFTINT_TIMER;
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cpu_kick_irq(cpu);
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}
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static void stick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->stick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("stick: fire\n");
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(cpu);
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}
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static void hstick_irq(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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CPUTimer *timer = env->hstick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("hstick: fire\n");
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(cpu);
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}
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static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
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{
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return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
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}
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static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
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{
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return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
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}
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void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
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{
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uint64_t real_count = count & ~timer->npt_mask;
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uint64_t npt_bit = count & timer->npt_mask;
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int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
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cpu_to_timer_ticks(real_count, timer->frequency);
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TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
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timer->name, real_count,
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timer->npt ? "disabled" : "enabled", timer);
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timer->npt = npt_bit ? 1 : 0;
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timer->clock_offset = vm_clock_offset;
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}
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uint64_t cpu_tick_get_count(CPUTimer *timer)
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{
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uint64_t real_count = timer_to_cpu_ticks(
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
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timer->frequency);
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TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
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timer->name, real_count,
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timer->npt ? "disabled" : "enabled", timer);
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if (timer->npt) {
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real_count |= timer->npt_mask;
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}
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return real_count;
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}
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void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
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{
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t real_limit = limit & ~timer->disabled_mask;
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timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
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int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
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timer->clock_offset;
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if (expires < now) {
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expires = now + 1;
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}
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TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
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"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
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timer->name, real_limit,
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timer->disabled ? "disabled" : "enabled",
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timer, limit,
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timer_to_cpu_ticks(now - timer->clock_offset,
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timer->frequency),
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timer_to_cpu_ticks(expires - now, timer->frequency));
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if (!real_limit) {
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TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
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timer->name);
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timer_del(timer->qtimer);
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} else if (timer->disabled) {
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timer_del(timer->qtimer);
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} else {
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timer_mod(timer->qtimer, expires);
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}
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}
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SPARCCPU *sparc64_cpu_devinit(const char *cpu_model,
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const char *default_cpu_model, uint64_t prom_addr)
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{
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SPARCCPU *cpu;
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CPUSPARCState *env;
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ResetData *reset_info;
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uint32_t tick_frequency = 100 * 1000000;
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uint32_t stick_frequency = 100 * 1000000;
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uint32_t hstick_frequency = 100 * 1000000;
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if (cpu_model == NULL) {
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cpu_model = default_cpu_model;
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}
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cpu = cpu_sparc_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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env = &cpu->env;
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env->tick = cpu_timer_create("tick", cpu, tick_irq,
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tick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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env->stick = cpu_timer_create("stick", cpu, stick_irq,
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stick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
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hstick_frequency, TICK_INT_DIS,
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TICK_NPT_MASK);
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reset_info = g_malloc0(sizeof(ResetData));
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reset_info->cpu = cpu;
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reset_info->prom_addr = prom_addr;
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qemu_register_reset(main_cpu_reset, reset_info);
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return cpu;
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}
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@ -38,25 +38,15 @@
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#include "hw/boards.h"
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#include "hw/nvram/sun_nvram.h"
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#include "hw/nvram/chrp_nvram.h"
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#include "hw/sparc/sparc64.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/sysbus.h"
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#include "hw/ide.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "sysemu/block-backend.h"
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#include "exec/address-spaces.h"
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#include "qemu/cutils.h"
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//#define DEBUG_IRQ
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//#define DEBUG_EBUS
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//#define DEBUG_TIMER
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#ifdef DEBUG_IRQ
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#define CPUIRQ_DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_EBUS
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#define EBUS_DPRINTF(fmt, ...) \
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@ -65,13 +55,6 @@
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#define EBUS_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define PROM_SIZE_MAX (4 * 1024 * 1024)
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@ -89,8 +72,6 @@
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#define IVEC_MAX 0x40
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#define TICK_MAX 0x7fffffffffffffffULL
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struct hwdef {
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const char * const default_cpu_model;
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uint16_t machine_id;
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@ -216,293 +197,11 @@ static uint64_t sun4u_load_kernel(const char *kernel_filename,
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return kernel_size;
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
|
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
|
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if (env->ivec_status & 0x20) {
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return;
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}
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cs = CPU(sparc_env_get_cpu(env));
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/* check if TM or SM in SOFTINT are set
|
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setting these also causes interrupt 14 */
|
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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|
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/* The bit corresponding to psrpil is (1<< psrpil), the next bit
|
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is (2 << psrpil). */
|
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if (pil < (2 << env->psrpil)){
|
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if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
|
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env->interrupt_index);
|
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env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (cpu_interrupts_enabled(env)) {
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 15; i > env->psrpil; i--) {
|
||||
if (pil & (1 << i)) {
|
||||
int old_interrupt = env->interrupt_index;
|
||||
int new_interrupt = TT_EXTINT | i;
|
||||
|
||||
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
|
||||
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
|
||||
CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
|
||||
"current %x >= pending %x\n",
|
||||
env->tl, cpu_tsptr(env)->tt, new_interrupt);
|
||||
} else if (old_interrupt != new_interrupt) {
|
||||
env->interrupt_index = new_interrupt;
|
||||
CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
|
||||
old_interrupt, new_interrupt);
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
|
||||
"current interrupt %x\n",
|
||||
pil, env->pil_in, env->softint, env->interrupt_index);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
}
|
||||
|
||||
static void cpu_kick_irq(SPARCCPU *cpu)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUSPARCState *env = &cpu->env;
|
||||
|
||||
cs->halted = 0;
|
||||
cpu_check_irqs(env);
|
||||
qemu_cpu_kick(cs);
|
||||
}
|
||||
|
||||
static void cpu_set_ivec_irq(void *opaque, int irq, int level)
|
||||
{
|
||||
SPARCCPU *cpu = opaque;
|
||||
CPUSPARCState *env = &cpu->env;
|
||||
CPUState *cs;
|
||||
|
||||
if (level) {
|
||||
if (!(env->ivec_status & 0x20)) {
|
||||
CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
|
||||
cs = CPU(cpu);
|
||||
cs->halted = 0;
|
||||
env->interrupt_index = TT_IVEC;
|
||||
env->ivec_status |= 0x20;
|
||||
env->ivec_data[0] = (0x1f << 6) | irq;
|
||||
env->ivec_data[1] = 0;
|
||||
env->ivec_data[2] = 0;
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
} else {
|
||||
if (env->ivec_status & 0x20) {
|
||||
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
|
||||
cs = CPU(cpu);
|
||||
env->ivec_status &= ~0x20;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
typedef struct ResetData {
|
||||
SPARCCPU *cpu;
|
||||
uint64_t prom_addr;
|
||||
} ResetData;
|
||||
|
||||
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
|
||||
QEMUBHFunc *cb, uint32_t frequency,
|
||||
uint64_t disabled_mask, uint64_t npt_mask)
|
||||
{
|
||||
CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
||||
|
||||
timer->name = name;
|
||||
timer->frequency = frequency;
|
||||
timer->disabled_mask = disabled_mask;
|
||||
timer->npt_mask = npt_mask;
|
||||
|
||||
timer->disabled = 1;
|
||||
timer->npt = 1;
|
||||
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
|
||||
timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
|
||||
|
||||
return timer;
|
||||
}
|
||||
|
||||
static void cpu_timer_reset(CPUTimer *timer)
|
||||
{
|
||||
timer->disabled = 1;
|
||||
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
|
||||
timer_del(timer->qtimer);
|
||||
}
|
||||
|
||||
static void main_cpu_reset(void *opaque)
|
||||
{
|
||||
ResetData *s = (ResetData *)opaque;
|
||||
CPUSPARCState *env = &s->cpu->env;
|
||||
static unsigned int nr_resets;
|
||||
|
||||
cpu_reset(CPU(s->cpu));
|
||||
|
||||
cpu_timer_reset(env->tick);
|
||||
cpu_timer_reset(env->stick);
|
||||
cpu_timer_reset(env->hstick);
|
||||
|
||||
env->gregs[1] = 0; // Memory start
|
||||
env->gregs[2] = ram_size; // Memory size
|
||||
env->gregs[3] = 0; // Machine description XXX
|
||||
if (nr_resets++ == 0) {
|
||||
/* Power on reset */
|
||||
env->pc = s->prom_addr + 0x20ULL;
|
||||
} else {
|
||||
env->pc = s->prom_addr + 0x40ULL;
|
||||
}
|
||||
env->npc = env->pc + 4;
|
||||
}
|
||||
|
||||
static void tick_irq(void *opaque)
|
||||
{
|
||||
SPARCCPU *cpu = opaque;
|
||||
CPUSPARCState *env = &cpu->env;
|
||||
|
||||
CPUTimer* timer = env->tick;
|
||||
|
||||
if (timer->disabled) {
|
||||
CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
||||
return;
|
||||
} else {
|
||||
CPUIRQ_DPRINTF("tick: fire\n");
|
||||
}
|
||||
|
||||
env->softint |= SOFTINT_TIMER;
|
||||
cpu_kick_irq(cpu);
|
||||
}
|
||||
|
||||
static void stick_irq(void *opaque)
|
||||
{
|
||||
SPARCCPU *cpu = opaque;
|
||||
CPUSPARCState *env = &cpu->env;
|
||||
|
||||
CPUTimer* timer = env->stick;
|
||||
|
||||
if (timer->disabled) {
|
||||
CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
||||
return;
|
||||
} else {
|
||||
CPUIRQ_DPRINTF("stick: fire\n");
|
||||
}
|
||||
|
||||
env->softint |= SOFTINT_STIMER;
|
||||
cpu_kick_irq(cpu);
|
||||
}
|
||||
|
||||
static void hstick_irq(void *opaque)
|
||||
{
|
||||
SPARCCPU *cpu = opaque;
|
||||
CPUSPARCState *env = &cpu->env;
|
||||
|
||||
CPUTimer* timer = env->hstick;
|
||||
|
||||
if (timer->disabled) {
|
||||
CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
||||
return;
|
||||
} else {
|
||||
CPUIRQ_DPRINTF("hstick: fire\n");
|
||||
}
|
||||
|
||||
env->softint |= SOFTINT_STIMER;
|
||||
cpu_kick_irq(cpu);
|
||||
}
|
||||
|
||||
static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
||||
{
|
||||
return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
|
||||
}
|
||||
|
||||
static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
||||
{
|
||||
return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
|
||||
}
|
||||
|
||||
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
||||
{
|
||||
uint64_t real_count = count & ~timer->npt_mask;
|
||||
uint64_t npt_bit = count & timer->npt_mask;
|
||||
|
||||
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
|
||||
cpu_to_timer_ticks(real_count, timer->frequency);
|
||||
|
||||
TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
|
||||
timer->name, real_count,
|
||||
timer->npt ? "disabled" : "enabled", timer);
|
||||
|
||||
timer->npt = npt_bit ? 1 : 0;
|
||||
timer->clock_offset = vm_clock_offset;
|
||||
}
|
||||
|
||||
uint64_t cpu_tick_get_count(CPUTimer *timer)
|
||||
{
|
||||
uint64_t real_count = timer_to_cpu_ticks(
|
||||
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
|
||||
timer->frequency);
|
||||
|
||||
TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
|
||||
timer->name, real_count,
|
||||
timer->npt ? "disabled" : "enabled", timer);
|
||||
|
||||
if (timer->npt) {
|
||||
real_count |= timer->npt_mask;
|
||||
}
|
||||
|
||||
return real_count;
|
||||
}
|
||||
|
||||
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
||||
{
|
||||
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
|
||||
uint64_t real_limit = limit & ~timer->disabled_mask;
|
||||
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
|
||||
|
||||
int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
|
||||
timer->clock_offset;
|
||||
|
||||
if (expires < now) {
|
||||
expires = now + 1;
|
||||
}
|
||||
|
||||
TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
||||
"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
||||
timer->name, real_limit,
|
||||
timer->disabled?"disabled":"enabled",
|
||||
timer, limit,
|
||||
timer_to_cpu_ticks(now - timer->clock_offset,
|
||||
timer->frequency),
|
||||
timer_to_cpu_ticks(expires - now, timer->frequency));
|
||||
|
||||
if (!real_limit) {
|
||||
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
||||
timer->name);
|
||||
timer_del(timer->qtimer);
|
||||
} else if (timer->disabled) {
|
||||
timer_del(timer->qtimer);
|
||||
} else {
|
||||
timer_mod(timer->qtimer, expires);
|
||||
}
|
||||
}
|
||||
|
||||
static void isa_irq_handler(void *opaque, int n, int level)
|
||||
{
|
||||
static const int isa_irq_to_ivec[16] = {
|
||||
@ -723,46 +422,6 @@ static const TypeInfo ram_info = {
|
||||
.class_init = ram_class_init,
|
||||
};
|
||||
|
||||
static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
|
||||
{
|
||||
SPARCCPU *cpu;
|
||||
CPUSPARCState *env;
|
||||
ResetData *reset_info;
|
||||
|
||||
uint32_t tick_frequency = 100*1000000;
|
||||
uint32_t stick_frequency = 100*1000000;
|
||||
uint32_t hstick_frequency = 100*1000000;
|
||||
|
||||
if (cpu_model == NULL) {
|
||||
cpu_model = hwdef->default_cpu_model;
|
||||
}
|
||||
cpu = cpu_sparc_init(cpu_model);
|
||||
if (cpu == NULL) {
|
||||
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
||||
exit(1);
|
||||
}
|
||||
env = &cpu->env;
|
||||
|
||||
env->tick = cpu_timer_create("tick", cpu, tick_irq,
|
||||
tick_frequency, TICK_INT_DIS,
|
||||
TICK_NPT_MASK);
|
||||
|
||||
env->stick = cpu_timer_create("stick", cpu, stick_irq,
|
||||
stick_frequency, TICK_INT_DIS,
|
||||
TICK_NPT_MASK);
|
||||
|
||||
env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
|
||||
hstick_frequency, TICK_INT_DIS,
|
||||
TICK_NPT_MASK);
|
||||
|
||||
reset_info = g_malloc0(sizeof(ResetData));
|
||||
reset_info->cpu = cpu;
|
||||
reset_info->prom_addr = hwdef->prom_addr;
|
||||
qemu_register_reset(main_cpu_reset, reset_info);
|
||||
|
||||
return cpu;
|
||||
}
|
||||
|
||||
static void sun4uv_init(MemoryRegion *address_space_mem,
|
||||
MachineState *machine,
|
||||
const struct hwdef *hwdef)
|
||||
@ -781,14 +440,15 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
|
||||
FWCfgState *fw_cfg;
|
||||
|
||||
/* init CPUs */
|
||||
cpu = cpu_devinit(machine->cpu_model, hwdef);
|
||||
cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model,
|
||||
hwdef->prom_addr);
|
||||
|
||||
/* set up devices */
|
||||
ram_init(0, machine->ram_size);
|
||||
|
||||
prom_init(hwdef->prom_addr, bios_name);
|
||||
|
||||
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
|
||||
ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX);
|
||||
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
|
||||
&pci_bus3, &pbm_irqs);
|
||||
pci_vga_init(pci_bus);
|
||||
|
||||
@ -36,7 +36,7 @@ typedef struct Sun4vRtc {
|
||||
static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr,
|
||||
unsigned size)
|
||||
{
|
||||
uint64_t val = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
|
||||
uint64_t val = get_clock_realtime() / NANOSECONDS_PER_SECOND;
|
||||
if (!(addr & 4ULL)) {
|
||||
/* accessing the high 32 bits */
|
||||
val >>= 32;
|
||||
|
||||
5
include/hw/sparc/sparc64.h
Normal file
5
include/hw/sparc/sparc64.h
Normal file
@ -0,0 +1,5 @@
|
||||
|
||||
SPARCCPU *sparc64_cpu_devinit(const char *cpu_model,
|
||||
const char *dflt_cpu_model, uint64_t prom_addr);
|
||||
|
||||
void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level);
|
||||
Loading…
Reference in New Issue
Block a user