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target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns
These instructions are part of pool1, see the grand tree above in the file. Q8ADD is part of pool1 too but belong to another category of instructions, thus will be made in later patches. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-8-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau
Philippe Mathieu-Daudé
parent
fc34c76f36
commit
ff7936f009
@ -358,6 +358,7 @@ enum {
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OPC_MXU__POOL00 = 0x03,
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OPC_MXU_S32MSUB = 0x04,
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OPC_MXU_S32MSUBU = 0x05,
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OPC_MXU__POOL01 = 0x06,
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OPC_MXU_D16MUL = 0x08,
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OPC_MXU_D16MAC = 0x0A,
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OPC_MXU__POOL04 = 0x10,
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@ -391,6 +392,18 @@ enum {
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OPC_MXU_Q8SLTU = 0x07,
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};
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/*
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* MXU pool 01
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*/
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enum {
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OPC_MXU_S32SLT = 0x00,
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OPC_MXU_D16SLT = 0x01,
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OPC_MXU_D16AVG = 0x02,
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OPC_MXU_D16AVGR = 0x03,
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OPC_MXU_Q8AVG = 0x04,
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OPC_MXU_Q8AVGR = 0x05,
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};
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/*
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* MXU pool 04 05 06 07 08 09 10 11
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*/
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@ -1152,11 +1165,15 @@ static void gen_mxu_S32XOR(DisasContext *ctx)
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/*
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* MXU instruction category max/min
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* MXU instruction category max/min/avg
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* S32MAX D16MAX Q8MAX
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* S32MIN D16MIN Q8MIN
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* S32SLT D16SLT Q8SLT
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* Q8SLTU
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* D16AVG Q8AVG
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* D16AVGR Q8AVGR
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*/
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/*
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@ -1462,6 +1479,199 @@ static void gen_mxu_q8slt(DisasContext *ctx, bool sltu)
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}
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}
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/*
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* S32SLT
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* Update XRa with the signed "set less than" comparison of XRb and XRc.
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* a.k.a. XRa = XRb < XRc ? 1 : 0;
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*/
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static void gen_mxu_S32SLT(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else {
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/* the most general case */
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tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1],
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mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]);
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}
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}
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/*
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* D16SLT
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* Update XRa with the signed "set less than" comparison of XRb and XRc
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* on per-word basis.
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* a.k.a. XRa[0..1] = XRb[0..1] < XRc[0..1] ? 1 : 0;
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*/
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static void gen_mxu_D16SLT(DisasContext *ctx)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGv t4 = tcg_temp_new();
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gen_load_mxu_gpr(t3, XRb);
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gen_load_mxu_gpr(t4, XRc);
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tcg_gen_sextract_tl(t0, t3, 16, 16);
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tcg_gen_sextract_tl(t1, t4, 16, 16);
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tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
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tcg_gen_shli_tl(t2, t0, 16);
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tcg_gen_sextract_tl(t0, t3, 0, 16);
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tcg_gen_sextract_tl(t1, t4, 0, 16);
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tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);
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tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0);
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}
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}
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/*
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* D16AVG
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* Update XRa with the signed average of XRb and XRc
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* on per-word basis, rounding down.
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* a.k.a. XRa[0..1] = (XRb[0..1] + XRc[0..1]) >> 1;
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*
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* D16AVGR
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* Update XRa with the signed average of XRb and XRc
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* on per-word basis, math rounding 4/5.
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* a.k.a. XRa[0..1] = (XRb[0..1] + XRc[0..1] + 1) >> 1;
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*/
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static void gen_mxu_d16avg(DisasContext *ctx, bool round45)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same registers -> just set destination to same */
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tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGv t4 = tcg_temp_new();
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gen_load_mxu_gpr(t3, XRb);
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gen_load_mxu_gpr(t4, XRc);
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tcg_gen_sextract_tl(t0, t3, 16, 16);
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tcg_gen_sextract_tl(t1, t4, 16, 16);
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tcg_gen_add_tl(t0, t0, t1);
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if (round45) {
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tcg_gen_addi_tl(t0, t0, 1);
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}
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tcg_gen_shli_tl(t2, t0, 15);
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tcg_gen_andi_tl(t2, t2, 0xffff0000);
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tcg_gen_sextract_tl(t0, t3, 0, 16);
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tcg_gen_sextract_tl(t1, t4, 0, 16);
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tcg_gen_add_tl(t0, t0, t1);
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if (round45) {
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tcg_gen_addi_tl(t0, t0, 1);
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}
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tcg_gen_shri_tl(t0, t0, 1);
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tcg_gen_deposit_tl(t2, t2, t0, 0, 16);
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gen_store_mxu_gpr(t2, XRa);
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}
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}
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/*
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* Q8AVG
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* Update XRa with the signed average of XRb and XRc
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* on per-byte basis, rounding down.
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* a.k.a. XRa[0..3] = (XRb[0..3] + XRc[0..3]) >> 1;
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*
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* Q8AVGR
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* Update XRa with the signed average of XRb and XRc
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* on per-word basis, math rounding 4/5.
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* a.k.a. XRa[0..3] = (XRb[0..3] + XRc[0..3] + 1) >> 1;
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*/
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static void gen_mxu_q8avg(DisasContext *ctx, bool round45)
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{
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uint32_t pad, XRc, XRb, XRa;
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pad = extract32(ctx->opcode, 21, 5);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to zero */
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tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRb == XRc)) {
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/* both operands same registers -> just set destination to same */
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tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
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} else {
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/* the most general case */
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGv t4 = tcg_temp_new();
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gen_load_mxu_gpr(t3, XRb);
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gen_load_mxu_gpr(t4, XRc);
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tcg_gen_movi_tl(t2, 0);
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for (int i = 0; i < 4; i++) {
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tcg_gen_extract_tl(t0, t3, 8 * i, 8);
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tcg_gen_extract_tl(t1, t4, 8 * i, 8);
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tcg_gen_add_tl(t0, t0, t1);
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if (round45) {
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tcg_gen_addi_tl(t0, t0, 1);
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}
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tcg_gen_shri_tl(t0, t0, 1);
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tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
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}
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gen_store_mxu_gpr(t2, XRa);
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}
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}
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/*
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* MXU instruction category: align
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@ -1769,6 +1979,35 @@ static bool decode_opc_mxu_s32madd_sub(DisasContext *ctx)
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return true;
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}
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static void decode_opc_mxu__pool01(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 18, 3);
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switch (opcode) {
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case OPC_MXU_S32SLT:
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gen_mxu_S32SLT(ctx);
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break;
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case OPC_MXU_D16SLT:
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gen_mxu_D16SLT(ctx);
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break;
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case OPC_MXU_D16AVG:
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gen_mxu_d16avg(ctx, false);
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break;
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case OPC_MXU_D16AVGR:
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gen_mxu_d16avg(ctx, true);
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break;
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case OPC_MXU_Q8AVG:
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gen_mxu_q8avg(ctx, false);
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break;
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case OPC_MXU_Q8AVGR:
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gen_mxu_q8avg(ctx, true);
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break;
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool04(DisasContext *ctx)
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{
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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@ -2015,6 +2254,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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case OPC_MXU_D16MAC:
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gen_mxu_d16mac(ctx);
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break;
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case OPC_MXU__POOL01:
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decode_opc_mxu__pool01(ctx);
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break;
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case OPC_MXU__POOL04:
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decode_opc_mxu__pool04(ctx);
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break;
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