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mips: Synchronize CP0 TCSTatus, Status and EntryHi
These registers share some of their fields. Writes to these fields should be visible through the corresponding mirror fields. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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Edgar E. Iglesias
parent
b93bbdcd69
commit
fe8dca8c3c
@ -774,6 +774,98 @@ static CPUState *mips_cpu_map_tc(int *tc)
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return other ? other : env;
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}
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/* The per VPE CP0_Status register shares some fields with the per TC
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CP0_TCStatus registers. These fields are wired to the same registers,
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so changes to either of them should be reflected on both registers.
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Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
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These helper call synchronizes the regs for a given cpu. */
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/* Called for updates to CP0_Status. */
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static void sync_c0_status(CPUState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & 0xff;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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/* Called for updates to CP0_TCStatus. */
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static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
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{
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uint32_t status;
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uint32_t tcu, tmx, tasid, tksu;
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uint32_t mask = ((1 << CP0St_CU3)
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| (1 << CP0St_CU2)
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| (1 << CP0St_CU1)
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| (1 << CP0St_CU0)
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| (1 << CP0St_MX)
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| (3 << CP0St_KSU));
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tcu = (v >> CP0TCSt_TCU0) & 0xf;
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tmx = (v >> CP0TCSt_TMX) & 0x1;
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tasid = v & 0xff;
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tksu = (v >> CP0TCSt_TKSU) & 0x3;
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status = tcu << CP0St_CU0;
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status |= tmx << CP0St_MX;
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status |= tksu << CP0St_KSU;
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cpu->CP0_Status &= ~mask;
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cpu->CP0_Status |= status;
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/* Sync the TASID with EntryHi. */
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cpu->CP0_EntryHi &= ~0xff;
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cpu->CP0_EntryHi = tasid;
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compute_hflags(cpu);
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}
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/* Called for updates to CP0_EntryHi. */
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static void sync_c0_entryhi(CPUState *cpu, int tc)
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{
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int32_t *tcst;
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uint32_t asid, v = cpu->CP0_EntryHi;
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asid = v & 0xff;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~0xff;
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*tcst |= asid;
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}
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/* CP0 helpers */
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target_ulong helper_mfc0_mvpcontrol (void)
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{
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@ -916,34 +1008,16 @@ target_ulong helper_mftc0_entryhi(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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int32_t tcstatus;
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if (other_tc == other->current_tc)
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tcstatus = other->active_tc.CP0_TCStatus;
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else
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tcstatus = other->tcs[other_tc].CP0_TCStatus;
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return (other->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
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return other->CP0_EntryHi;
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}
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target_ulong helper_mftc0_status(void)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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target_ulong t0;
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int32_t tcstatus;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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if (other_tc == other->current_tc)
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tcstatus = other->active_tc.CP0_TCStatus;
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else
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tcstatus = other->tcs[other_tc].CP0_TCStatus;
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t0 = other->CP0_Status & ~0xf1000018;
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t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
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t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
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t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
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return t0;
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return other->CP0_Status;
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}
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target_ulong helper_mfc0_lladdr (void)
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@ -1129,9 +1203,8 @@ void helper_mtc0_tcstatus (target_ulong arg1)
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newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
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// TODO: Sync with CP0_Status.
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env->active_tc.CP0_TCStatus = newval;
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sync_c0_tcstatus(env, env->current_tc, newval);
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}
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void helper_mttc0_tcstatus (target_ulong arg1)
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@ -1139,12 +1212,11 @@ void helper_mttc0_tcstatus (target_ulong arg1)
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUState *other = mips_cpu_map_tc(&other_tc);
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// TODO: Sync with CP0_Status.
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCStatus = arg1;
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else
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other->tcs[other_tc].CP0_TCStatus = arg1;
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sync_c0_tcstatus(other, other_tc, arg1);
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}
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void helper_mtc0_tcbind (target_ulong arg1)
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@ -1348,8 +1420,7 @@ void helper_mtc0_entryhi (target_ulong arg1)
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old = env->CP0_EntryHi;
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env->CP0_EntryHi = val;
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
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env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
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sync_c0_entryhi(env, env->current_tc);
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}
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/* If the ASID changes, flush qemu's TLB. */
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if ((old & 0xFF) != (val & 0xFF))
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@ -1359,17 +1430,10 @@ void helper_mtc0_entryhi (target_ulong arg1)
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void helper_mttc0_entryhi(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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int32_t tcstatus;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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other->CP0_EntryHi = (other->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
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if (other_tc == other->current_tc) {
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tcstatus = (other->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
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other->active_tc.CP0_TCStatus = tcstatus;
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} else {
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tcstatus = (other->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
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other->tcs[other_tc].CP0_TCStatus = tcstatus;
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}
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other->CP0_EntryHi = arg1;
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sync_c0_entryhi(other, other_tc);
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}
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void helper_mtc0_compare (target_ulong arg1)
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@ -1385,7 +1449,12 @@ void helper_mtc0_status (target_ulong arg1)
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val = arg1 & mask;
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old = env->CP0_Status;
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env->CP0_Status = (env->CP0_Status & ~mask) | val;
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compute_hflags(env);
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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sync_c0_status(env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
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qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
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old, old & env->CP0_Cause & CP0Ca_IP_mask,
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@ -1403,17 +1472,10 @@ void helper_mtc0_status (target_ulong arg1)
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void helper_mttc0_status(target_ulong arg1)
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{
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
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CPUState *other = mips_cpu_map_tc(&other_tc);
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other->CP0_Status = arg1 & ~0xf1000018;
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tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
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tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
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tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
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if (other_tc == other->current_tc)
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other->active_tc.CP0_TCStatus = tcstatus;
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else
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other->tcs[other_tc].CP0_TCStatus = tcstatus;
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sync_c0_status(other, other_tc);
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}
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void helper_mtc0_intctl (target_ulong arg1)
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