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target-ppc: convert altivec load/store to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
a0d7d5a776
commit
fe1e5c53fd
@ -542,7 +542,6 @@ struct CPUPPCState {
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*/
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uint64_t t0_64, t1_64, t2_64;
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#endif
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ppc_avr_t avr0, avr1, avr2;
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/* general purpose registers */
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target_ulong gpr[32];
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@ -54,10 +54,6 @@ register target_ulong T2 asm(AREG3);
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#define T1_64 T1
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#define T2_64 T2
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#endif
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/* Provision for Altivec */
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#define AVR0 (env->avr0)
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#define AVR1 (env->avr1)
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#define AVR2 (env->avr2)
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#define FT0 (env->ft0)
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#define FT1 (env->ft1)
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@ -642,66 +642,6 @@ void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
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RETURN();
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}
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/* Altivec vector extension */
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#if defined(WORDS_BIGENDIAN)
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#define VR_DWORD0 0
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#define VR_DWORD1 1
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#else
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#define VR_DWORD0 1
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#define VR_DWORD1 0
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#endif
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void OPPROTO glue(op_vr_lvx, MEMSUFFIX) (void)
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{
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AVR0.u64[VR_DWORD0] = glue(ldu64, MEMSUFFIX)((uint32_t)T0);
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AVR0.u64[VR_DWORD1] = glue(ldu64, MEMSUFFIX)((uint32_t)T0 + 8);
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}
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void OPPROTO glue(op_vr_lvx_le, MEMSUFFIX) (void)
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{
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AVR0.u64[VR_DWORD1] = glue(ldu64r, MEMSUFFIX)((uint32_t)T0);
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AVR0.u64[VR_DWORD0] = glue(ldu64r, MEMSUFFIX)((uint32_t)T0 + 8);
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}
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void OPPROTO glue(op_vr_stvx, MEMSUFFIX) (void)
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{
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glue(st64, MEMSUFFIX)((uint32_t)T0, AVR0.u64[VR_DWORD0]);
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glue(st64, MEMSUFFIX)((uint32_t)T0 + 8, AVR0.u64[VR_DWORD1]);
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}
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void OPPROTO glue(op_vr_stvx_le, MEMSUFFIX) (void)
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{
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glue(st64r, MEMSUFFIX)((uint32_t)T0, AVR0.u64[VR_DWORD1]);
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glue(st64r, MEMSUFFIX)((uint32_t)T0 + 8, AVR0.u64[VR_DWORD0]);
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}
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#if defined(TARGET_PPC64)
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void OPPROTO glue(op_vr_lvx_64, MEMSUFFIX) (void)
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{
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AVR0.u64[VR_DWORD0] = glue(ldu64, MEMSUFFIX)((uint64_t)T0);
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AVR0.u64[VR_DWORD1] = glue(ldu64, MEMSUFFIX)((uint64_t)T0 + 8);
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}
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void OPPROTO glue(op_vr_lvx_le_64, MEMSUFFIX) (void)
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{
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AVR0.u64[VR_DWORD1] = glue(ldu64r, MEMSUFFIX)((uint64_t)T0);
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AVR0.u64[VR_DWORD0] = glue(ldu64r, MEMSUFFIX)((uint64_t)T0 + 8);
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}
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void OPPROTO glue(op_vr_stvx_64, MEMSUFFIX) (void)
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{
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glue(st64, MEMSUFFIX)((uint64_t)T0, AVR0.u64[VR_DWORD0]);
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glue(st64, MEMSUFFIX)((uint64_t)T0 + 8, AVR0.u64[VR_DWORD1]);
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}
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void OPPROTO glue(op_vr_stvx_le_64, MEMSUFFIX) (void)
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{
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glue(st64r, MEMSUFFIX)((uint64_t)T0, AVR0.u64[VR_DWORD1]);
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glue(st64r, MEMSUFFIX)((uint64_t)T0 + 8, AVR0.u64[VR_DWORD0]);
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}
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#endif
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#undef VR_DWORD0
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#undef VR_DWORD1
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/* SPE extension */
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#define _PPC_SPE_LD_OP(name, op) \
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void OPPROTO glue(glue(op_spe_l, name), MEMSUFFIX) (void) \
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@ -77,7 +77,6 @@ static TCGv cpu_T[3];
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static TCGv_i64 cpu_T64[3];
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#endif
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static TCGv_i64 cpu_FT[2];
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static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3];
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#include "gen-icount.h"
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@ -122,19 +121,6 @@ void ppc_translate_init(void)
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cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, ft1), "FT1");
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cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr0.u64[0]), "AVR0H");
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cpu_AVRl[0] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr0.u64[1]), "AVR0L");
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cpu_AVRh[1] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr1.u64[0]), "AVR1H");
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cpu_AVRl[1] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr1.u64[1]), "AVR1L");
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cpu_AVRh[2] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr2.u64[0]), "AVR2H");
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cpu_AVRl[2] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr2.u64[1]), "AVR2L");
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p = cpu_reg_names;
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for (i = 0; i < 8; i++) {
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@ -162,13 +148,23 @@ void ppc_translate_init(void)
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p += (i < 10) ? 4 : 5;
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sprintf(p, "avr%dH", i);
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#ifdef WORDS_BIGENDIAN
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cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr[i].u64[0]), p);
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offsetof(CPUState, avr[i].u64[0]), p);
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#else
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cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr[i].u64[1]), p);
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#endif
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p += (i < 10) ? 6 : 7;
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sprintf(p, "avr%dL", i);
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#ifdef WORDS_BIGENDIAN
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cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr[i].u64[1]), p);
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offsetof(CPUState, avr[i].u64[1]), p);
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#else
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cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, avr[i].u64[0]), p);
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#endif
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p += (i < 10) ? 6 : 7;
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}
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@ -5939,61 +5935,59 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
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/*** Altivec vector extension ***/
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/* Altivec registers moves */
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static always_inline void gen_load_avr(int t, int reg) {
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tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
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tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
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}
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static always_inline void gen_store_avr(int reg, int t) {
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tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
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tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
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}
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#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
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#define OP_VR_LD_TABLE(name) \
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static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
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GEN_MEM_FUNCS(vr_l##name), \
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};
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#define OP_VR_ST_TABLE(name) \
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static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
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GEN_MEM_FUNCS(vr_st##name), \
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};
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#define GEN_VR_LDX(name, opc2, opc3) \
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GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
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GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
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{ \
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TCGv EA; \
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if (unlikely(!ctx->altivec_enabled)) { \
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GEN_EXCP_NO_VR(ctx); \
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return; \
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} \
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gen_addr_reg_index(cpu_T[0], ctx); \
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op_vr_ldst(vr_l##name); \
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gen_store_avr(rD(ctx->opcode), 0); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(EA, ctx); \
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tcg_gen_andi_tl(EA, EA, ~0xf); \
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if (ctx->mem_idx & 1) { \
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gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
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} else { \
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gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
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} \
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tcg_temp_free(EA); \
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}
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#define GEN_VR_STX(name, opc2, opc3) \
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GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
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{ \
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TCGv EA; \
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if (unlikely(!ctx->altivec_enabled)) { \
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GEN_EXCP_NO_VR(ctx); \
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return; \
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} \
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gen_addr_reg_index(cpu_T[0], ctx); \
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gen_load_avr(0, rS(ctx->opcode)); \
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op_vr_ldst(vr_st##name); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(EA, ctx); \
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tcg_gen_andi_tl(EA, EA, ~0xf); \
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if (ctx->mem_idx & 1) { \
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gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
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} else { \
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gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
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} \
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tcg_temp_free(EA); \
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}
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OP_VR_LD_TABLE(vx);
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GEN_VR_LDX(vx, 0x07, 0x03);
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GEN_VR_LDX(lvx, 0x07, 0x03);
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/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
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#define gen_op_vr_lvxl gen_op_vr_lvx
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GEN_VR_LDX(vxl, 0x07, 0x0B);
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GEN_VR_LDX(lvxl, 0x07, 0x0B);
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OP_VR_ST_TABLE(vx);
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GEN_VR_STX(vx, 0x07, 0x07);
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GEN_VR_STX(svx, 0x07, 0x07);
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/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
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#define gen_op_vr_stvxl gen_op_vr_stvx
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GEN_VR_STX(vxl, 0x07, 0x0F);
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GEN_VR_STX(svxl, 0x07, 0x0F);
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/*** SPE extension ***/
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/* Register moves */
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