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target/arm: Log CPU index in 'Taking exception' log

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In an SMP system it can be unclear which CPU is taking an exception;
add the CPU index (which is the same value used in the TCG 'Trace
%d:' logging) to the "Taking exception" log line to clarify it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-01-22 18:24:31 +00:00
parent 0166f5c466
commit fc6177af11
3 changed files with 8 additions and 5 deletions
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9
target/arm/helper.c
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@ -9317,8 +9317,10 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
return target_el;
}
void arm_log_exception(int idx)
void arm_log_exception(CPUState *cs)
{
int idx = cs->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *exc = NULL;
static const char * const excnames[] = {
@ -9352,7 +9354,8 @@ void arm_log_exception(int idx)
if (!exc) {
exc = "unknown";
}
qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n",
idx, exc, cs->cpu_index);
}
}
@ -10185,7 +10188,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
assert(!arm_feature(env, ARM_FEATURE_M));
arm_log_exception(cs->exception_index);
arm_log_exception(cs);
qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
new_el);
if (qemu_loglevel_mask(CPU_LOG_INT)

2
target/arm/internals.h
View File

@ -1130,7 +1130,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
__attribute__((nonnull));
void arm_log_exception(int idx);
void arm_log_exception(CPUState *cs);
#endif /* !CONFIG_USER_ONLY */

2
target/arm/m_helper.c
View File

@ -2206,7 +2206,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
uint32_t lr;
bool ignore_stackfaults;
arm_log_exception(cs->exception_index);
arm_log_exception(cs);
/*
* For exceptions we just mark as pending on the NVIC, and let that