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acpi: split out piix4 smbus routines from acpi.c into pm_smbus.c
Split out piix4 smbus routines from acpi.c into pm_smbus.c and use it. The split out smbus emulation will be used later. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Isaku Yamahata
Blue Swirl
parent
dc6839100e
commit
fc0bdd995c
@ -195,6 +195,7 @@ obj-i386-y += cirrus_vga.o apic.o ioapic.o piix_pci.o
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obj-i386-y += vmmouse.o vmport.o hpet.o
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obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
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obj-i386-y += debugcon.o multiboot.o
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obj-i386-y += pm_smbus.o
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# shared objects
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obj-ppc-y = ppc.o
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@ -220,6 +221,7 @@ obj-mips-y += dma.o vga.o i8259.o
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obj-mips-y += g364fb.o jazz_led.o
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obj-mips-y += gt64xxx.o pckbd.o mc146818rtc.o
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obj-mips-y += piix4.o cirrus_vga.o
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obj-mips-y += pm_smbus.o
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obj-microblaze-y = petalogix_s3adsp1800_mmu.o
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164
hw/acpi.c
164
hw/acpi.c
@ -17,6 +17,7 @@
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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@ -39,15 +40,9 @@ typedef struct PIIX4PMState {
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uint8_t apms;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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i2c_bus *smbus;
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uint8_t smb_stat;
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uint8_t smb_ctl;
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uint8_t smb_cmd;
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uint8_t smb_addr;
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uint8_t smb_data0;
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uint8_t smb_data1;
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uint8_t smb_data[32];
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uint8_t smb_index;
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PMSMBus smb;
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qemu_irq irq;
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qemu_irq cmos_s3;
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qemu_irq smi_irq;
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@ -68,14 +63,6 @@ typedef struct PIIX4PMState {
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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static PIIX4PMState *pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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@ -282,141 +269,6 @@ static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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#endif
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}
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static void smb_transaction(PIIX4PMState *s)
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{
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus;
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0:
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smbus_quick_command(bus, addr, read);
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break;
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case 0x1:
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr);
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} else {
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smbus_send_byte(bus, addr, cmd);
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}
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break;
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case 0x2:
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd);
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0);
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}
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break;
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case 0x3:
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if (read) {
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uint16_t val;
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val = smbus_read_word(bus, addr, cmd);
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s->smb_data0 = val;
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s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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}
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break;
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case 0x5:
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
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} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
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}
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break;
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default:
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goto error;
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}
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return;
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error:
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s->smb_stat |= 0x04;
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}
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static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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s->smb_index = 0;
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break;
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case SMBHSTCNT:
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s->smb_ctl = val;
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if (val & 0x40)
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smb_transaction(s);
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break;
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case SMBHSTCMD:
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s->smb_cmd = val;
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break;
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case SMBHSTADD:
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s->smb_addr = val;
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break;
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case SMBHSTDAT0:
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s->smb_data0 = val;
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break;
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case SMBHSTDAT1:
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s->smb_data1 = val;
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break;
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case SMBBLKDAT:
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s->smb_data[s->smb_index++] = val;
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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break;
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}
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}
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static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case SMBHSTSTS:
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val = s->smb_stat;
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break;
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case SMBHSTCNT:
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s->smb_index = 0;
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val = s->smb_ctl & 0x1f;
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break;
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case SMBHSTCMD:
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val = s->smb_cmd;
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break;
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case SMBHSTADD:
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val = s->smb_addr;
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break;
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case SMBHSTDAT0:
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val = s->smb_data0;
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break;
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case SMBHSTDAT1:
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val = s->smb_data1;
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break;
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case SMBBLKDAT:
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val = s->smb_data[s->smb_index++];
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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@ -545,8 +397,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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pci_conf[0x90] = smb_io_base | 1;
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pci_conf[0x91] = smb_io_base >> 8;
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pci_conf[0xd2] = 0x09;
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register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
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register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
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register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
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register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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@ -554,13 +406,13 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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vmstate_register(0, &vmstate_acpi, s);
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s->smbus = i2c_init_bus(NULL, "i2c");
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pm_smbus_init(NULL, &s->smb);
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s->irq = sci_irq;
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s->cmos_s3 = cmos_s3;
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s->smi_irq = smi_irq;
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qemu_register_reset(piix4_reset, s);
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return s->smbus;
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return s->smb.smbus;
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}
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#define GPE_BASE 0xafe0
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178
hw/pm_smbus.c
Normal file
178
hw/pm_smbus.c
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@ -0,0 +1,178 @@
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/*
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* PC SMBus implementation
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* splitted from acpi.c
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "i2c.h"
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#include "smbus.h"
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#include "kvm.h"
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/* no save/load? */
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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static void smb_transaction(PMSMBus *s)
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{
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus;
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0:
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smbus_quick_command(bus, addr, read);
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break;
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case 0x1:
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr);
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} else {
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smbus_send_byte(bus, addr, cmd);
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}
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break;
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case 0x2:
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd);
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0);
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}
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break;
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case 0x3:
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if (read) {
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uint16_t val;
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val = smbus_read_word(bus, addr, cmd);
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s->smb_data0 = val;
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s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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}
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break;
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case 0x5:
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
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} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
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}
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break;
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default:
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goto error;
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}
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return;
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error:
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s->smb_stat |= 0x04;
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}
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void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PMSMBus *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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s->smb_index = 0;
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break;
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case SMBHSTCNT:
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s->smb_ctl = val;
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if (val & 0x40)
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smb_transaction(s);
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break;
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case SMBHSTCMD:
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s->smb_cmd = val;
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break;
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case SMBHSTADD:
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s->smb_addr = val;
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break;
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case SMBHSTDAT0:
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s->smb_data0 = val;
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break;
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case SMBHSTDAT1:
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s->smb_data1 = val;
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break;
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case SMBBLKDAT:
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s->smb_data[s->smb_index++] = val;
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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break;
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}
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}
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uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
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{
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PMSMBus *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case SMBHSTSTS:
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val = s->smb_stat;
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break;
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case SMBHSTCNT:
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s->smb_index = 0;
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val = s->smb_ctl & 0x1f;
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break;
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case SMBHSTCMD:
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val = s->smb_cmd;
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break;
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case SMBHSTADD:
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val = s->smb_addr;
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break;
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case SMBHSTDAT0:
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val = s->smb_data0;
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break;
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case SMBHSTDAT1:
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val = s->smb_data1;
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break;
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case SMBBLKDAT:
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val = s->smb_data[s->smb_index++];
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if (s->smb_index > 31)
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s->smb_index = 0;
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break;
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default:
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val = 0;
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break;
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}
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#ifdef DEBUG
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printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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return val;
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}
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void pm_smbus_init(DeviceState *parent, PMSMBus *smb)
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{
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smb->smbus = i2c_init_bus(parent, "i2c");
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}
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21
hw/pm_smbus.h
Normal file
21
hw/pm_smbus.h
Normal file
@ -0,0 +1,21 @@
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#ifndef PM_SMBUS_H
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#define PM_SMBUS_H
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typedef struct PMSMBus {
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i2c_bus *smbus;
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uint8_t smb_stat;
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uint8_t smb_ctl;
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uint8_t smb_cmd;
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uint8_t smb_addr;
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uint8_t smb_data0;
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uint8_t smb_data1;
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uint8_t smb_data[32];
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uint8_t smb_index;
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} PMSMBus;
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void pm_smbus_init(DeviceState *parent, PMSMBus *smb);
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void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val);
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uint32_t smb_ioport_readb(void *opaque, uint32_t addr);
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#endif /* !PM_SMBUS_H */
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