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target-microblaze: dec_barrel: Add BSEFI
Add support for BSEFI. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -660,7 +660,8 @@ static void dec_div(DisasContext *dc)
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static void dec_barrel(DisasContext *dc)
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{
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TCGv t0;
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bool s, t;
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unsigned int imm_w, imm_s;
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bool s, t, e = false;
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if ((dc->tb_flags & MSR_EE_FLAG)
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&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
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@ -670,27 +671,44 @@ static void dec_barrel(DisasContext *dc)
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return;
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}
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if (dc->type_b) {
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/* Insert and extract are only available in immediate mode. */
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e = extract32(dc->imm, 14, 1);
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}
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s = extract32(dc->imm, 10, 1);
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t = extract32(dc->imm, 9, 1);
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imm_w = extract32(dc->imm, 6, 5);
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imm_s = extract32(dc->imm, 0, 5);
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LOG_DIS("bs%s%s r%d r%d r%d\n",
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LOG_DIS("bs%s%s%s r%d r%d r%d\n",
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e ? "e" : "",
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s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
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t0 = tcg_temp_new();
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tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
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tcg_gen_andi_tl(t0, t0, 31);
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if (s) {
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tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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} else {
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if (t) {
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tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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if (e) {
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if (imm_w + imm_s > 32 || imm_w == 0) {
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/* These inputs have an undefined behavior. */
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qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n",
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imm_w, imm_s);
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} else {
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tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
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}
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} else {
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t0 = tcg_temp_new();
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tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
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tcg_gen_andi_tl(t0, t0, 31);
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if (s) {
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tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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} else {
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if (t) {
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tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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} else {
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tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
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}
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}
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tcg_temp_free(t0);
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}
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tcg_temp_free(t0);
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}
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static void dec_bit(DisasContext *dc)
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