mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-26 12:23:36 +08:00
Code Issues Packages Projects Releases Wiki Activity

pc: acpi: q35: move PCI0._OSC() method into SSDT

Browse Source 
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov 2015-12-28 18:02:54 +01:00 committed by Michael S. Tsirkin
parent e9fce79861
commit f97a88a85e
2 changed files with 56 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
hw/i386/acpi-build.c
View File

@ -1896,6 +1896,54 @@ static void build_piix4_pci_hotplug(Aml *table)
aml_append(table, scope);
}
static Aml *build_q35_osc_method(void)
{
Aml *if_ctx;
Aml *if_ctx2;
Aml *else_ctx;
Aml *method;
Aml *a_cwd1 = aml_name("CDW1");
Aml *a_ctrl = aml_name("CTRL");
method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
if_ctx = aml_if(aml_equal(
aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
/*
* Always allow native PME, AER (no dependencies)
* Never allow SHPC (no SHPC controller in this system)
*/
aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
/* Unknown revision */
aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
aml_append(if_ctx, if_ctx2);
if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
/* Capabilities bits were masked */
aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
aml_append(if_ctx, if_ctx2);
/* Update DWORD3 in the buffer */
aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
aml_append(method, if_ctx);
else_ctx = aml_else();
/* Unrecognized UUID */
aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
aml_append(method, else_ctx);
aml_append(method, aml_return(aml_arg(3)));
return method;
}
static void
build_ssdt(GArray *table_data, GArray *linker,
@ -1934,6 +1982,14 @@ build_ssdt(GArray *table_data, GArray *linker,
build_piix4_pci_hotplug(ssdt);
build_piix4_pci0_int(ssdt);
} else {
sb_scope = aml_scope("_SB");
scope = aml_scope("PCI0");
aml_append(scope, aml_name_decl("SUPP", aml_int(0)));
aml_append(scope, aml_name_decl("CTRL", aml_int(0)));
aml_append(scope, build_q35_osc_method());
aml_append(sb_scope, scope);
aml_append(ssdt, sb_scope);
build_hpet_aml(ssdt);
build_q35_isa_bridge(ssdt);
build_isa_devices_aml(ssdt);

57
hw/i386/q35-acpi-dsdt.dsl
View File

@ -53,63 +53,6 @@ DefinitionBlock (
Name(_CID, EisaId("PNP0A03"))
Name(_ADR, 0x00)
Name(_UID, 1)
External(ISA, DeviceObj)
// _OSC: based on sample of ACPI3.0b spec
Name(SUPP, 0) // PCI _OSC Support Field value
Name(CTRL, 0) // PCI _OSC Control Field value
Method(_OSC, 4) {
// Create DWORD-addressable fields from the Capabilities Buffer
CreateDWordField(Arg3, 0, CDW1)
// Check for proper UUID
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
// Create DWORD-addressable fields from the Capabilities Buffer
CreateDWordField(Arg3, 4, CDW2)
CreateDWordField(Arg3, 8, CDW3)
// Save Capabilities DWORD2 & 3
Store(CDW2, SUPP)
Store(CDW3, CTRL)
// Always allow native PME, AER (no dependencies)
// Never allow SHPC (no SHPC controller in this system)
And(CTRL, 0x1D, CTRL)
#if 0 // For now, nothing to do
If (Not(And(CDW1, 1))) { // Query flag clear?
// Disable GPEs for features granted native control.
If (And(CTRL, 0x01)) { // Hot plug control granted?
Store(0, HPCE) // clear the hot plug SCI enable bit
Store(1, HPCS) // clear the hot plug SCI status bit
}
If (And(CTRL, 0x04)) { // PME control granted?
Store(0, PMCE) // clear the PME SCI enable bit
Store(1, PMCS) // clear the PME SCI status bit
}
If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
// Set status to not restore PCI Express cap structure
// upon resume from S3
Store(1, S3CR)
}
}
#endif
If (LNotEqual(Arg1, One)) {
// Unknown revision
Or(CDW1, 0x08, CDW1)
}
If (LNotEqual(CDW3, CTRL)) {
// Capabilities bits were masked
Or(CDW1, 0x10, CDW1)
}
// Update DWORD3 in the buffer
Store(CTRL, CDW3)
} Else {
Or(CDW1, 4, CDW1) // Unrecognized UUID
}
Return (Arg3)
}
}
}
}