mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-12-12 05:03:42 +08:00
Code Issues Packages Projects Releases Wiki Activity

hw/mips/gt64xxx: Trace accesses to ISD registers

Browse Source 
Trace all accesses to Internal Space Decode (ISD) registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-03-04 19:02:56 +01:00
parent 1b3422bde2
commit f8ead0d7bd
2 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/mips/gt64xxx_pci.c
View File

@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr = addr >> 2;
trace_gt64120_write(addr, val);
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque,
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
trace_gt64120_read(addr, val);
return val;
}

2
hw/mips/trace-events
View File

@ -1,4 +1,6 @@
# gt64xxx_pci.c
gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64