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target-m68k: Split gen_lea and gen_ea
Provide gen_lea_mode and gen_ea_mode, where the mode can be specified manually, rather than taken from the instruction. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-3-git-send-email-rth@twiddle.net>
This commit is contained in:
Richard Henderson
Laurent Vivier
parent
8a1e52b69d
commit
f84aab269d
@ -697,37 +697,37 @@ static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
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/* Generate code for an "effective address". Does not adjust the base
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register for autoincrement addressing modes. */
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static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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int opsize)
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static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
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int mode, int reg0, int opsize)
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{
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TCGv reg;
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TCGv tmp;
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uint16_t ext;
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uint32_t offset;
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switch ((insn >> 3) & 7) {
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switch (mode) {
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case 0: /* Data register direct. */
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case 1: /* Address register direct. */
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return NULL_QREG;
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case 2: /* Indirect register */
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case 3: /* Indirect postincrement. */
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return AREG(insn, 0);
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return get_areg(s, reg0);
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case 4: /* Indirect predecrememnt. */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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tmp = tcg_temp_new();
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tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
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return tmp;
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case 5: /* Indirect displacement. */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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tmp = tcg_temp_new();
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ext = read_im16(env, s);
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tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
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return tmp;
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case 6: /* Indirect index + displacement. */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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return gen_lea_indexed(env, s, reg);
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case 7: /* Other */
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switch (insn & 7) {
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switch (reg0) {
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case 0: /* Absolute short. */
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offset = (int16_t)read_im16(env, s);
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return tcg_const_i32(offset);
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@ -749,39 +749,26 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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return NULL_QREG;
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}
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/* Helper function for gen_ea. Reuse the computed address between the
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for read/write operands. */
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static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
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uint16_t insn, int opsize, TCGv val,
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TCGv *addrp, ea_what what)
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static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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int opsize)
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{
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TCGv tmp;
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if (addrp && what == EA_STORE) {
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tmp = *addrp;
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} else {
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tmp = gen_lea(env, s, insn, opsize);
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if (IS_NULL_QREG(tmp))
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return tmp;
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if (addrp)
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*addrp = tmp;
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}
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return gen_ldst(s, opsize, tmp, val, what);
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int mode = extract32(insn, 3, 3);
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int reg0 = REG(insn, 0);
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return gen_lea_mode(env, s, mode, reg0, opsize);
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}
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/* Generate code to load/store a value from/into an EA. If VAL > 0 this is
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/* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
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a write otherwise it is a read (0 == sign extend, -1 == zero extend).
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ADDRP is non-null for readwrite operands. */
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static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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int opsize, TCGv val, TCGv *addrp, ea_what what)
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static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
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int opsize, TCGv val, TCGv *addrp, ea_what what)
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{
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TCGv reg;
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TCGv result;
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uint32_t offset;
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TCGv reg, tmp, result;
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int32_t offset;
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switch ((insn >> 3) & 7) {
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switch (mode) {
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case 0: /* Data register direct. */
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reg = DREG(insn, 0);
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reg = cpu_dregs[reg0];
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if (what == EA_STORE) {
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gen_partset_reg(opsize, reg, val);
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return store_dummy;
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@ -789,7 +776,7 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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return gen_extend(reg, opsize, what == EA_LOADS);
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}
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case 1: /* Address register direct. */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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if (what == EA_STORE) {
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tcg_gen_mov_i32(reg, val);
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return store_dummy;
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@ -797,45 +784,56 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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return gen_extend(reg, opsize, what == EA_LOADS);
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}
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case 2: /* Indirect register */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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return gen_ldst(s, opsize, reg, val, what);
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case 3: /* Indirect postincrement. */
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reg = AREG(insn, 0);
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reg = get_areg(s, reg0);
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result = gen_ldst(s, opsize, reg, val, what);
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if (what == EA_STORE || !addrp) {
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TCGv tmp = tcg_temp_new();
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tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
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delay_set_areg(s, REG(insn, 0), tmp, true);
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delay_set_areg(s, reg0, tmp, true);
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}
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return result;
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case 4: /* Indirect predecrememnt. */
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{
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TCGv tmp;
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if (addrp && what == EA_STORE) {
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tmp = *addrp;
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} else {
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tmp = gen_lea(env, s, insn, opsize);
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if (IS_NULL_QREG(tmp))
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return tmp;
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if (addrp)
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*addrp = tmp;
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if (addrp && what == EA_STORE) {
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tmp = *addrp;
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} else {
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tmp = gen_lea_mode(env, s, mode, reg0, opsize);
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if (IS_NULL_QREG(tmp)) {
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return tmp;
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}
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result = gen_ldst(s, opsize, tmp, val, what);
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if (what == EA_STORE || !addrp) {
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delay_set_areg(s, REG(insn, 0), tmp, false);
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if (addrp) {
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*addrp = tmp;
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}
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}
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result = gen_ldst(s, opsize, tmp, val, what);
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if (what == EA_STORE || !addrp) {
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delay_set_areg(s, reg0, tmp, false);
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}
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return result;
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case 5: /* Indirect displacement. */
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case 6: /* Indirect index + displacement. */
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return gen_ea_once(env, s, insn, opsize, val, addrp, what);
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do_indirect:
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if (addrp && what == EA_STORE) {
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tmp = *addrp;
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} else {
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tmp = gen_lea_mode(env, s, mode, reg0, opsize);
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if (IS_NULL_QREG(tmp)) {
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return tmp;
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}
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if (addrp) {
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*addrp = tmp;
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}
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}
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return gen_ldst(s, opsize, tmp, val, what);
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case 7: /* Other */
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switch (insn & 7) {
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switch (reg0) {
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case 0: /* Absolute short. */
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case 1: /* Absolute long. */
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case 2: /* pc displacement */
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case 3: /* pc index+displacement. */
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return gen_ea_once(env, s, insn, opsize, val, addrp, what);
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goto do_indirect;
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case 4: /* Immediate. */
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/* Sign extend values for consistency. */
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switch (opsize) {
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@ -868,6 +866,14 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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return NULL_QREG;
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}
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static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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int opsize, TCGv val, TCGv *addrp, ea_what what)
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{
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int mode = extract32(insn, 3, 3);
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int reg0 = REG(insn, 0);
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return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
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}
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typedef struct {
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TCGCond tcond;
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bool g1;
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