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https://github.com/qemu/qemu.git
synced 2024-12-18 09:43:38 +08:00
Reorganize the CPUPPCState structure to group features.
Add #ifdef to avoid compiling not relevant resources: - MMU related stuff for user-mode only targets - PowerPC 64 only resources for PowerPC 32 targets - embedded PowerPC extensions for non-ppcemb targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
d26bfc9a1b
commit
f2e63a42c9
@ -495,9 +495,14 @@ struct CPUPPCState {
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int access_type; /* when a memory exception occurs, the access
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type is stored here */
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/* MMU context */
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/* MMU context - only relevant for full system emulation */
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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/* Address space register */
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target_ulong asr;
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/* PowerPC 64 SLB area */
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int slb_nr;
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#endif
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/* segment registers */
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target_ulong sdr1;
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target_ulong sr[16];
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@ -505,24 +510,6 @@ struct CPUPPCState {
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int nb_BATs;
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target_ulong DBAT[2][8];
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target_ulong IBAT[2][8];
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/* Other registers */
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/* Special purpose registers */
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target_ulong spr[1024];
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/* Altivec registers */
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ppc_avr_t avr[32];
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uint32_t vscr;
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/* SPE registers */
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ppc_gpr_t spe_acc;
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float_status spe_status;
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uint32_t spe_fscr;
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/* Internal devices resources */
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/* Time base and decrementer */
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ppc_tb_t *tb_env;
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/* Device control registers */
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ppc_dcr_t *dcr_env;
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/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
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int nb_tlb; /* Total number of TLB */
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int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
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@ -533,8 +520,27 @@ struct CPUPPCState {
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ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
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/* 403 dedicated access protection registers */
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target_ulong pb[4];
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/* PowerPC 64 SLB area */
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int slb_nr;
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#endif
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/* Other registers */
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/* Special purpose registers */
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target_ulong spr[1024];
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ppc_spr_t spr_cb[1024];
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/* Altivec registers */
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ppc_avr_t avr[32];
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uint32_t vscr;
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#if defined(TARGET_PPCEMB)
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/* SPE registers */
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ppc_gpr_t spe_acc;
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float_status spe_status;
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uint32_t spe_fscr;
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#endif
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/* Internal devices resources */
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/* Time base and decrementer */
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ppc_tb_t *tb_env;
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/* Device control registers */
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ppc_dcr_t *dcr_env;
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int dcache_line_size;
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int icache_line_size;
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@ -570,8 +576,7 @@ struct CPUPPCState {
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/* Those resources are used only during code translation */
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/* Next instruction pointer */
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target_ulong nip;
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/* SPR translation callbacks */
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ppc_spr_t spr_cb[1024];
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/* opcode handlers */
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opc_handler_t *opcodes[0x40];
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@ -6448,9 +6448,11 @@ void cpu_dump_state (CPUState *env, FILE *f,
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if ((i & (RFPL - 1)) == (RFPL - 1))
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cpu_fprintf(f, "\n");
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}
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#if !defined(CONFIG_USER_ONLY)
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cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
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"SDR1 " REGX "\n",
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env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
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#endif
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#undef RGPL
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#undef RFPL
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@ -533,6 +533,7 @@ static void gen_spr_ne_601 (CPUPPCState *env)
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/* BATs 0-3 */
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static void gen_low_BATs (CPUPPCState *env)
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{
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#if !defined(CONFIG_USER_ONLY)
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spr_register(env, SPR_IBAT0U, "IBAT0U",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_ibat, &spr_write_ibatu,
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@ -598,11 +599,13 @@ static void gen_low_BATs (CPUPPCState *env)
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&spr_read_dbat, &spr_write_dbatl,
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0x00000000);
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env->nb_BATs += 4;
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#endif
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}
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/* BATs 4-7 */
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static void gen_high_BATs (CPUPPCState *env)
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{
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#if !defined(CONFIG_USER_ONLY)
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spr_register(env, SPR_IBAT4U, "IBAT4U",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_ibat_h, &spr_write_ibatu_h,
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@ -668,6 +671,7 @@ static void gen_high_BATs (CPUPPCState *env)
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&spr_read_dbat_h, &spr_write_dbatl_h,
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0x00000000);
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env->nb_BATs += 4;
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#endif
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}
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/* Generic PowerPC time base */
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@ -694,6 +698,7 @@ static void gen_tbl (CPUPPCState *env)
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/* Softare table search registers */
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static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
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{
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = nb_tlbs;
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env->nb_ways = nb_ways;
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env->id_tlbs = 1;
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@ -725,6 +730,7 @@ static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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#endif
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}
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/* SPR common to MPC755 and G2 */
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@ -1105,6 +1111,7 @@ static void gen_spr_601 (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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spr_register(env, SPR_IBAT0U, "IBAT0U",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_601_ubat, &spr_write_601_ubatu,
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@ -1138,6 +1145,7 @@ static void gen_spr_601 (CPUPPCState *env)
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&spr_read_601_ubat, &spr_write_601_ubatl,
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0x00000000);
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env->nb_BATs = 4;
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#endif
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}
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static void gen_spr_74xx (CPUPPCState *env)
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@ -1238,6 +1246,7 @@ static void gen_l3_ctrl (CPUPPCState *env)
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static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
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{
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = nb_tlbs;
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env->nb_ways = nb_ways;
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env->id_tlbs = 1;
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@ -1256,6 +1265,7 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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#endif
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}
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/* PowerPC BookE SPR */
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@ -1512,6 +1522,7 @@ static void gen_spr_BookE (CPUPPCState *env)
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/* FSL storage control registers */
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static void gen_spr_BookE_FSL (CPUPPCState *env)
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{
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#if !defined(CONFIG_USER_ONLY)
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/* TLB assist registers */
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_MAS0, "MAS0",
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@ -1605,6 +1616,7 @@ static void gen_spr_BookE_FSL (CPUPPCState *env)
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default:
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break;
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}
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#endif
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}
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/* SPR specific to PowerPC 440 implementation */
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@ -2616,9 +2628,11 @@ static void init_proc_401x2 (CPUPPCState *env)
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gen_spr_401x2(env);
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gen_spr_compress(env);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_4xx_softmmu(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2674,9 +2688,11 @@ static void init_proc_IOP480 (CPUPPCState *env)
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gen_spr_401x2(env);
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gen_spr_compress(env);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_4xx_softmmu(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2744,9 +2760,11 @@ static void init_proc_403GCX (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_4xx_softmmu(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2785,9 +2803,11 @@ static void init_proc_405 (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_4xx_softmmu(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2832,9 +2852,11 @@ static void init_proc_440EP (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2860,9 +2882,11 @@ static void init_proc_440GP (CPUPPCState *env)
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gen_spr_BookE(env);
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gen_spr_440(env);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2889,9 +2913,11 @@ static void init_proc_440x4 (CPUPPCState *env)
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gen_spr_BookE(env);
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gen_spr_440(env);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2935,9 +2961,11 @@ static void init_proc_440x5 (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -2987,9 +3015,11 @@ static void init_proc_460 (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -3042,9 +3072,11 @@ static void init_proc_460F (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -3097,9 +3129,11 @@ static void init_proc_e500 (CPUPPCState *env)
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gen_spr_BookE(env);
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/* Memory management */
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gen_spr_BookE_FSL(env);
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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@ -3167,10 +3201,11 @@ static void init_proc_601 (CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 2;
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env->id_tlbs = 0;
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env->id_tlbs = 0;
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#endif
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init_excp_601(env);
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env->dcache_line_size = 64;
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env->icache_line_size = 64;
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@ -4041,7 +4076,9 @@ static void init_proc_970 (CPUPPCState *env)
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#if !defined(CONFIG_USER_ONLY)
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env->excp_prefix = 0xFFF00000;
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#endif
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#if !defined(CONFIG_USER_ONLY)
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env->slb_nr = 32;
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#endif
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init_excp_970(env);
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env->dcache_line_size = 128;
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env->icache_line_size = 128;
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@ -4112,7 +4149,9 @@ static void init_proc_970FX (CPUPPCState *env)
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#if !defined(CONFIG_USER_ONLY)
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env->excp_prefix = 0xFFF00000;
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#endif
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#if !defined(CONFIG_USER_ONLY)
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env->slb_nr = 32;
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#endif
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init_excp_970(env);
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env->dcache_line_size = 128;
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env->icache_line_size = 128;
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@ -4183,7 +4222,9 @@ static void init_proc_970GX (CPUPPCState *env)
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#if !defined(CONFIG_USER_ONLY)
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env->excp_prefix = 0xFFF00000;
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#endif
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#if !defined(CONFIG_USER_ONLY)
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env->slb_nr = 32;
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#endif
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init_excp_970(env);
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env->dcache_line_size = 128;
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env->icache_line_size = 128;
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@ -5729,11 +5770,11 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
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env->excp_prefix = 0x00000000;
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env->ivor_mask = 0x00000000;
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env->ivpr_mask = 0x00000000;
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#endif
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/* Default MMU definitions */
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env->nb_BATs = 0;
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env->nb_tlb = 0;
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env->nb_ways = 0;
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#endif
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/* Register SPR common to all PowerPC implementations */
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gen_spr_generic(env);
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spr_register(env, SPR_PVR, "PVR",
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@ -5743,6 +5784,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
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/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
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(*def->init_proc)(env);
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/* Allocate TLBs buffer when needed */
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#if !defined(CONFIG_USER_ONLY)
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if (env->nb_tlb != 0) {
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int nb_tlb = env->nb_tlb;
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if (env->id_tlbs != 0)
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@ -5751,7 +5793,6 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
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/* Pre-compute some useful values */
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env->tlb_per_way = env->nb_tlb / env->nb_ways;
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}
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#if !defined(CONFIG_USER_ONLY)
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if (env->irq_inputs == NULL) {
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fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
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" Attempt Qemu to crash very soon !\n");
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@ -6171,11 +6212,13 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
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printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
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" MMU model : %s\n",
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def->name, def->pvr, def->msr_mask, mmu_model);
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#if !defined(CONFIG_USER_ONLY)
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if (env->tlb != NULL) {
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printf(" %d %s TLB in %d ways\n",
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env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
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env->nb_ways);
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}
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#endif
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printf(" Exceptions model : %s\n"
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" Bus model : %s\n",
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excp_model, bus_model);
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