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target-arm: Report correct syndrome for FPEXC32_EL2 traps
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
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@ -1334,6 +1334,11 @@ typedef enum CPAccessResult {
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/* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
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CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
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CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
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/* Access fails and results in an exception syndrome for an FP access,
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* trapped directly to EL2 or EL3
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*/
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CP_ACCESS_TRAP_FP_EL2 = 7,
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CP_ACCESS_TRAP_FP_EL3 = 8,
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} CPAccessResult;
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/* Access functions for coprocessor registers. These cannot fail and
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@ -3011,10 +3011,10 @@ static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
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return CP_ACCESS_TRAP_EL2;
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return CP_ACCESS_TRAP_FP_EL2;
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}
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if (env->cp15.cptr_el[3] & CPTR_TFP) {
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return CP_ACCESS_TRAP_EL3;
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return CP_ACCESS_TRAP_FP_EL3;
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}
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return CP_ACCESS_OK;
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}
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@ -500,6 +500,19 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
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target_el = 3;
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syndrome = syn_uncategorized();
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break;
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case CP_ACCESS_TRAP_FP_EL2:
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target_el = 2;
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/* Since we are an implementation that takes exceptions on a trapped
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* conditional insn only if the insn has passed its condition code
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* check, we take the IMPDEF choice to always report CV=1 COND=0xe
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* (which is also the required value for AArch64 traps).
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*/
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syndrome = syn_fp_access_trap(1, 0xe, false);
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break;
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case CP_ACCESS_TRAP_FP_EL3:
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target_el = 3;
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syndrome = syn_fp_access_trap(1, 0xe, false);
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break;
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default:
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g_assert_not_reached();
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}
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