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target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..

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..for address calculation instead address registers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2015-03-27 14:55:22 +01:00
parent 627f91b1f8
commit f1fdaf5529
1 changed files with 4 additions and 4 deletions
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8
target-tricore/translate.c
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@ -4509,14 +4509,14 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEA_I_POSTINC: case OPC2_32_BO_CACHEA_I_POSTINC:
/* instruction to access the cache, but we still need to handle /* instruction to access the cache, but we still need to handle
the addressing mode */ the addressing mode */
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break; break;
case OPC2_32_BO_CACHEA_WI_PREINC: case OPC2_32_BO_CACHEA_WI_PREINC:
case OPC2_32_BO_CACHEA_W_PREINC: case OPC2_32_BO_CACHEA_W_PREINC:
case OPC2_32_BO_CACHEA_I_PREINC: case OPC2_32_BO_CACHEA_I_PREINC:
/* instruction to access the cache, but we still need to handle /* instruction to access the cache, but we still need to handle
the addressing mode */ the addressing mode */
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break; break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF:
@ -4526,13 +4526,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) { if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */ } /* TODO: else raise illegal opcode trap */
break; break;
case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) { if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */ } /* TODO: else raise illegal opcode trap */
break; break;
case OPC2_32_BO_ST_A_SHORTOFF: case OPC2_32_BO_ST_A_SHORTOFF: