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* Refactor next-cube interrupt and register handling into a proper QOM device
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This commit is contained in:
Peter Maydell
commit
f1fcb6851a
@ -28,6 +28,7 @@
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#include "qapi/error.h"
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#include "ui/console.h"
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#include "target/m68k/cpu.h"
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#include "migration/vmstate.h"
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/* #define DEBUG_NEXT */
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#ifdef DEBUG_NEXT
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@ -73,19 +74,27 @@ typedef struct NextRtc {
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struct NeXTState {
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MachineState parent;
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uint32_t int_mask;
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uint32_t int_status;
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uint8_t scsi_csr_1;
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uint8_t scsi_csr_2;
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next_dma dma[10];
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qemu_irq *scsi_irq;
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qemu_irq scsi_dma;
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qemu_irq scsi_reset;
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qemu_irq *fd_irq;
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};
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#define TYPE_NEXT_PC "next-pc"
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OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC)
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/* NeXT Peripheral Controller */
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struct NeXTPC {
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SysBusDevice parent_obj;
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M68kCPU *cpu;
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MemoryRegion mmiomem;
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MemoryRegion scrmem;
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uint32_t scr1;
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uint32_t scr2;
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uint8_t scsi_csr_1;
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uint8_t scsi_csr_2;
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uint32_t int_mask;
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uint32_t int_status;
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NextRtc rtc;
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};
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@ -110,7 +119,7 @@ static const uint8_t rtc_ram2[32] = {
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#define SCR2_RTDATA 0x4
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#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
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static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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static void nextscr2_write(NeXTPC *s, uint32_t val, int size)
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{
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static int led;
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static int phase;
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@ -244,7 +253,7 @@ static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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old_scr2 = scr2_2;
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}
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static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readb(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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case 0xc000:
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@ -274,7 +283,7 @@ static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
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}
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}
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static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readw(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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default:
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@ -283,7 +292,7 @@ static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
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}
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}
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static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
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static uint32_t mmio_readl(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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case 0x7000:
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@ -306,7 +315,7 @@ static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
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}
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}
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static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0xd003:
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@ -318,12 +327,12 @@ static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
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}
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static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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DPRINTF("MMIO Write W\n");
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}
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static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
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static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0x7000:
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@ -348,15 +357,15 @@ static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
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static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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return mmio_readb(ns, addr);
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return mmio_readb(s, addr);
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case 2:
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return mmio_readw(ns, addr);
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return mmio_readw(s, addr);
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case 4:
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return mmio_readl(ns, addr);
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return mmio_readl(s, addr);
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default:
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g_assert_not_reached();
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}
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@ -365,17 +374,17 @@ static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
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static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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mmio_writeb(ns, addr, value);
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mmio_writeb(s, addr, value);
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break;
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case 2:
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mmio_writew(ns, addr, value);
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mmio_writew(s, addr, value);
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break;
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case 4:
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mmio_writel(ns, addr, value);
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mmio_writel(s, addr, value);
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break;
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default:
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g_assert_not_reached();
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@ -390,7 +399,7 @@ static const MemoryRegionOps mmio_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint32_t scr_readb(NeXTState *s, hwaddr addr)
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static uint32_t scr_readb(NeXTPC *s, hwaddr addr)
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{
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switch (addr) {
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case 0x14108:
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@ -424,13 +433,13 @@ static uint32_t scr_readb(NeXTState *s, hwaddr addr)
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}
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}
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static uint32_t scr_readw(NeXTState *s, hwaddr addr)
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static uint32_t scr_readw(NeXTPC *s, hwaddr addr)
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{
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DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr);
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return 0;
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}
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static uint32_t scr_readl(NeXTState *s, hwaddr addr)
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static uint32_t scr_readl(NeXTPC *s, hwaddr addr)
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{
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DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr);
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return 0;
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@ -443,7 +452,7 @@ static uint32_t scr_readl(NeXTState *s, hwaddr addr)
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#define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
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#define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
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static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value)
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static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value)
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{
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switch (addr) {
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case 0x14108:
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@ -521,27 +530,27 @@ static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value)
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}
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}
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static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value)
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static void scr_writew(NeXTPC *s, hwaddr addr, uint32_t value)
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{
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DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value);
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}
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static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value)
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static void scr_writel(NeXTPC *s, hwaddr addr, uint32_t value)
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{
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DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value);
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}
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static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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return scr_readb(ns, addr);
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return scr_readb(s, addr);
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case 2:
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return scr_readw(ns, addr);
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return scr_readw(s, addr);
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case 4:
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return scr_readl(ns, addr);
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return scr_readl(s, addr);
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default:
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g_assert_not_reached();
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}
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@ -550,17 +559,17 @@ static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size)
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static void scr_writefn(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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NeXTPC *s = NEXT_PC(opaque);
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switch (size) {
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case 1:
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scr_writeb(ns, addr, value);
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scr_writeb(s, addr, value);
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break;
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case 2:
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scr_writew(ns, addr, value);
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scr_writew(s, addr, value);
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break;
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case 4:
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scr_writel(ns, addr, value);
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scr_writel(s, addr, value);
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break;
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default:
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g_assert_not_reached();
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@ -720,15 +729,11 @@ static const MemoryRegionOps dma_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/*
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* TODO: set the shift numbers as values in the enum, so the first switch
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* will not be needed
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*/
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void next_irq(void *opaque, int number, int level)
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static void next_irq(void *opaque, int number, int level)
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{
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M68kCPU *cpu = opaque;
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NeXTPC *s = NEXT_PC(opaque);
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M68kCPU *cpu = s->cpu;
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int shift = 0;
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NeXTState *ns = NEXT_MACHINE(qdev_get_machine());
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/* first switch sets interupt status */
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/* DPRINTF("IRQ %i\n",number); */
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@ -783,14 +788,14 @@ void next_irq(void *opaque, int number, int level)
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* this HAS to be wrong, the interrupt handlers in mach and together
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* int_status and int_mask and return if there is a hit
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*/
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if (ns->int_mask & (1 << shift)) {
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if (s->int_mask & (1 << shift)) {
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DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
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/* return; */
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}
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/* second switch triggers the correct interrupt */
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if (level) {
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ns->int_status |= 1 << shift;
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s->int_status |= 1 << shift;
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switch (number) {
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/* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
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@ -819,24 +824,13 @@ void next_irq(void *opaque, int number, int level)
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break;
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}
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} else {
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ns->int_status &= ~(1 << shift);
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s->int_status &= ~(1 << shift);
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cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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}
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static void next_serial_irq(void *opaque, int n, int level)
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static void next_escc_init(DeviceState *pcdev)
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{
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/* DPRINTF("SCC IRQ NUM %i\n",n); */
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if (n) {
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next_irq(opaque, NEXT_SCC_DMA_I, level);
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} else {
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next_irq(opaque, NEXT_SCC_I, level);
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}
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}
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static void next_escc_init(M68kCPU *cpu)
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{
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qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, cpu, 2);
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DeviceState *dev;
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SysBusDevice *s;
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@ -852,25 +846,113 @@ static void next_escc_init(M68kCPU *cpu)
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_connect_irq(s, 0, ser_irq[0]);
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sysbus_connect_irq(s, 1, ser_irq[1]);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(pcdev, NEXT_SCC_I));
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sysbus_connect_irq(s, 1, qdev_get_gpio_in(pcdev, NEXT_SCC_DMA_I));
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sysbus_mmio_map(s, 0, 0x2118000);
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}
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static void next_pc_reset(DeviceState *dev)
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{
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NeXTPC *s = NEXT_PC(dev);
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/* Set internal registers to initial values */
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/* 0x0000XX00 << vital bits */
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s->scr1 = 0x00011102;
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s->scr2 = 0x00ff0c80;
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s->rtc.status = 0x90;
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/* Load RTC RAM - TODO: provide possibility to load contents from file */
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memcpy(s->rtc.ram, rtc_ram2, 32);
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}
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static void next_pc_realize(DeviceState *dev, Error **errp)
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{
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NeXTPC *s = NEXT_PC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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qdev_init_gpio_in(dev, next_irq, NEXT_NUM_IRQS);
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memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s,
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"next.mmio", 0xD0000);
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memory_region_init_io(&s->scrmem, OBJECT(s), &scr_ops, s,
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"next.scr", 0x20000);
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sysbus_init_mmio(sbd, &s->mmiomem);
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sysbus_init_mmio(sbd, &s->scrmem);
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}
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/*
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* If the m68k CPU implemented its inbound irq lines as GPIO lines
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* rather than via the m68k_set_irq_level() function we would not need
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* this cpu link property and could instead provide outbound IRQ lines
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* that the board could wire up to the CPU.
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*/
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static Property next_pc_properties[] = {
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DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription next_rtc_vmstate = {
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.name = "next-rtc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(ram, NextRtc, 32),
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VMSTATE_UINT8(command, NextRtc),
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VMSTATE_UINT8(value, NextRtc),
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VMSTATE_UINT8(status, NextRtc),
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VMSTATE_UINT8(control, NextRtc),
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VMSTATE_UINT8(retval, NextRtc),
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VMSTATE_END_OF_LIST()
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},
|
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};
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static const VMStateDescription next_pc_vmstate = {
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.name = "next-pc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(scr1, NeXTPC),
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VMSTATE_UINT32(scr2, NeXTPC),
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VMSTATE_UINT32(int_mask, NeXTPC),
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VMSTATE_UINT32(int_status, NeXTPC),
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VMSTATE_UINT8(scsi_csr_1, NeXTPC),
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VMSTATE_UINT8(scsi_csr_2, NeXTPC),
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VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NextRtc),
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VMSTATE_END_OF_LIST()
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},
|
||||
};
|
||||
|
||||
static void next_pc_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->desc = "NeXT Peripheral Controller";
|
||||
dc->realize = next_pc_realize;
|
||||
dc->reset = next_pc_reset;
|
||||
device_class_set_props(dc, next_pc_properties);
|
||||
dc->vmsd = &next_pc_vmstate;
|
||||
}
|
||||
|
||||
static const TypeInfo next_pc_info = {
|
||||
.name = TYPE_NEXT_PC,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(NeXTPC),
|
||||
.class_init = next_pc_class_init,
|
||||
};
|
||||
|
||||
static void next_cube_init(MachineState *machine)
|
||||
{
|
||||
M68kCPU *cpu;
|
||||
CPUM68KState *env;
|
||||
MemoryRegion *rom = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *scrmem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *dmamem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *bmapm1 = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *bmapm2 = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *sysmem = get_system_memory();
|
||||
const char *bios_name = machine->firmware ?: ROM_FILE;
|
||||
NeXTState *ns = NEXT_MACHINE(machine);
|
||||
DeviceState *dev;
|
||||
DeviceState *pcdev;
|
||||
|
||||
/* Initialize the cpu core */
|
||||
cpu = M68K_CPU(cpu_create(machine->cpu_type));
|
||||
@ -884,14 +966,10 @@ static void next_cube_init(MachineState *machine)
|
||||
env->vbr = 0;
|
||||
env->sr = 0x2700;
|
||||
|
||||
/* Set internal registers to initial values */
|
||||
/* 0x0000XX00 << vital bits */
|
||||
ns->scr1 = 0x00011102;
|
||||
ns->scr2 = 0x00ff0c80;
|
||||
ns->rtc.status = 0x90;
|
||||
|
||||
/* Load RTC RAM - TODO: provide possibility to load contents from file */
|
||||
memcpy(ns->rtc.ram, rtc_ram2, 32);
|
||||
/* Peripheral Controller */
|
||||
pcdev = qdev_new(TYPE_NEXT_PC);
|
||||
object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort);
|
||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal);
|
||||
|
||||
/* 64MB RAM starting at 0x04000000 */
|
||||
memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
|
||||
@ -902,9 +980,10 @@ static void next_cube_init(MachineState *machine)
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
|
||||
|
||||
/* MMIO */
|
||||
memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
|
||||
0xD0000);
|
||||
memory_region_add_subregion(sysmem, 0x02000000, mmiomem);
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000);
|
||||
|
||||
/* BMAP IO - acts as a catch-all for now */
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000);
|
||||
|
||||
/* BMAP memory */
|
||||
memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64,
|
||||
@ -914,11 +993,6 @@ static void next_cube_init(MachineState *machine)
|
||||
memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64);
|
||||
memory_region_add_subregion(sysmem, 0x820c0000, bmapm2);
|
||||
|
||||
/* BMAP IO - acts as a catch-all for now */
|
||||
memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr",
|
||||
0x20000);
|
||||
memory_region_add_subregion(sysmem, 0x02100000, scrmem);
|
||||
|
||||
/* KBD */
|
||||
dev = qdev_new(TYPE_NEXTKBD);
|
||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||||
@ -946,7 +1020,7 @@ static void next_cube_init(MachineState *machine)
|
||||
}
|
||||
|
||||
/* Serial */
|
||||
next_escc_init(cpu);
|
||||
next_escc_init(pcdev);
|
||||
|
||||
/* TODO: */
|
||||
/* Network */
|
||||
@ -978,6 +1052,7 @@ static const TypeInfo next_typeinfo = {
|
||||
static void next_register_type(void)
|
||||
{
|
||||
type_register_static(&next_typeinfo);
|
||||
type_register_static(&next_pc_info);
|
||||
}
|
||||
|
||||
type_init(next_register_type)
|
||||
|
||||
@ -1,3 +1,13 @@
|
||||
/*
|
||||
* NeXT Cube
|
||||
*
|
||||
* Copyright (c) 2011 Bryce Lanham
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundation; either version 2 of the License,
|
||||
* or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef NEXT_CUBE_H
|
||||
#define NEXT_CUBE_H
|
||||
@ -39,9 +49,8 @@ enum next_irqs {
|
||||
NEXT_ENRX_DMA_I,
|
||||
NEXT_SCSI_DMA_I,
|
||||
NEXT_SCC_DMA_I,
|
||||
NEXT_SND_I
|
||||
NEXT_SND_I,
|
||||
NEXT_NUM_IRQS
|
||||
};
|
||||
|
||||
void next_irq(void *opaque, int number, int level);
|
||||
|
||||
#endif /* NEXT_CUBE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user