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target/loongarch: Implement vsigncov

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This patch includes:
- VSIGNCOV.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-20-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:45 +08:00
parent 3734ad9370
commit f0e395dfb0
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 75 additions and 0 deletions
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5
target/loongarch/disas.c
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@ -1079,3 +1079,8 @@ INSN_LSX(vexth_hu_bu, vv)
INSN_LSX(vexth_wu_hu, vv)
INSN_LSX(vexth_du_wu, vv)
INSN_LSX(vexth_qu_du, vv)
INSN_LSX(vsigncov_b, vvv)
INSN_LSX(vsigncov_h, vvv)
INSN_LSX(vsigncov_w, vvv)
INSN_LSX(vsigncov_d, vvv)

5
target/loongarch/helper.h
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@ -338,3 +338,8 @@ DEF_HELPER_3(vexth_hu_bu, void, env, i32, i32)
DEF_HELPER_3(vexth_wu_hu, void, env, i32, i32)
DEF_HELPER_3(vexth_du_wu, void, env, i32, i32)
DEF_HELPER_3(vexth_qu_du, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vsigncov_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

53
target/loongarch/insn_trans/trans_lsx.c.inc
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@ -2814,3 +2814,56 @@ TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu)
TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu)
TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu)
TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du)
static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t1, zero;
t1 = tcg_temp_new_vec_matching(t);
zero = tcg_constant_vec_matching(t, vece, 0);
tcg_gen_neg_vec(vece, t1, b);
tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, a, zero, t1, b);
tcg_gen_cmpsel_vec(TCG_COND_EQ, vece, t, a, zero, zero, t);
}
static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_neg_vec, INDEX_op_cmpsel_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vsigncov,
.fno = gen_helper_vsigncov_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vsigncov,
.fno = gen_helper_vsigncov_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vsigncov,
.fno = gen_helper_vsigncov_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vsigncov,
.fno = gen_helper_vsigncov_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}
TRANS(vsigncov_b, gvec_vvv, MO_8, do_vsigncov)
TRANS(vsigncov_h, gvec_vvv, MO_16, do_vsigncov)
TRANS(vsigncov_w, gvec_vvv, MO_32, do_vsigncov)
TRANS(vsigncov_d, gvec_vvv, MO_64, do_vsigncov)

5
target/loongarch/insns.decode
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@ -778,3 +778,8 @@ vexth_hu_bu 0111 00101001 11101 11100 ..... ..... @vv
vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv
vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv
vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv
vsigncov_b 0111 00010010 11100 ..... ..... ..... @vvv
vsigncov_h 0111 00010010 11101 ..... ..... ..... @vvv
vsigncov_w 0111 00010010 11110 ..... ..... ..... @vvv
vsigncov_d 0111 00010010 11111 ..... ..... ..... @vvv

7
target/loongarch/lsx_helper.c
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@ -662,3 +662,10 @@ VEXTH(vexth_d_w, 64, D, W)
VEXTH(vexth_hu_bu, 16, UH, UB)
VEXTH(vexth_wu_hu, 32, UW, UH)
VEXTH(vexth_du_wu, 64, UD, UW)
#define DO_SIGNCOV(a, b) (a == 0 ? 0 : a < 0 ? -b : b)
DO_3OP(vsigncov_b, 8, B, DO_SIGNCOV)
DO_3OP(vsigncov_h, 16, H, DO_SIGNCOV)
DO_3OP(vsigncov_w, 32, W, DO_SIGNCOV)
DO_3OP(vsigncov_d, 64, D, DO_SIGNCOV)