mirror of
https://github.com/qemu/qemu.git
synced 2024-11-25 11:53:39 +08:00
tcg/optimize: improve known-zero bits for 32-bit ops
The shl_i32 op might set some bits of the unused 32 high bits of the mask. Fix that by clearing the unused 32 high bits for all 32-bit ops except load/store which operate on tl values. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
3031244b01
commit
f096dc9618
@ -783,6 +783,12 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr,
|
||||
break;
|
||||
}
|
||||
|
||||
/* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit
|
||||
results */
|
||||
if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) {
|
||||
mask &= 0xffffffffu;
|
||||
}
|
||||
|
||||
if (mask == 0) {
|
||||
assert(def->nb_oargs == 1);
|
||||
s->gen_opc_buf[op_index] = op_to_movi(op);
|
||||
|
Loading…
Reference in New Issue
Block a user