mirror of
https://github.com/qemu/qemu.git
synced 2024-11-24 19:33:39 +08:00
TCX 24 bit model support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2710 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
b9652ca3a5
commit
eee0b8367b
@ -234,8 +234,12 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
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dma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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slavio_irq[hwdef->le_irq], iommu);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
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hwdef->vram_size, graphic_width, graphic_height);
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hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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231
hw/tcx.c
231
hw/tcx.c
@ -31,14 +31,16 @@ typedef struct TCXState {
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uint32_t addr;
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DisplayState *ds;
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uint8_t *vram;
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ram_addr_t vram_offset;
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uint16_t width, height;
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uint32_t *vram24, *cplane;
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ram_addr_t vram_offset, vram24_offset, cplane_offset;
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uint16_t width, height, depth;
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uint8_t r[256], g[256], b[256];
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uint32_t palette[256];
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uint8_t dac_index, dac_state;
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} TCXState;
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static void tcx_screen_dump(void *opaque, const char *filename);
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static void tcx24_screen_dump(void *opaque, const char *filename);
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/* XXX: unify with vga draw line functions */
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static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
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@ -121,6 +123,57 @@ static void tcx_draw_line8(TCXState *s1, uint8_t *d,
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}
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}
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static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
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const uint8_t *s, int width,
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const uint32_t *cplane,
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const uint32_t *s24)
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{
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int x;
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uint8_t val;
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uint32_t *p = (uint32_t *)d;
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uint32_t dval;
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for(x = 0; x < width; x++, s++, s24++) {
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if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct
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dval = bswap32(*s24) & 0x00ffffff;
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} else {
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val = *s;
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dval = s1->palette[val];
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}
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*p++ = dval;
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}
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}
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static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24,
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ram_addr_t cpage)
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{
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int ret;
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unsigned int off;
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ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
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for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
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ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
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ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
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}
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return ret;
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}
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static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
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ram_addr_t page_max, ram_addr_t page24,
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ram_addr_t cpage)
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{
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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page_min -= ts->vram_offset;
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page_max -= ts->vram_offset;
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cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG);
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}
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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VGA... */
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static void tcx_update_display(void *opaque)
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@ -201,6 +254,82 @@ static void tcx_update_display(void *opaque)
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}
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}
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static void tcx24_update_display(void *opaque)
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{
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TCXState *ts = opaque;
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ram_addr_t page, page_min, page_max, cpage, page24;
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int y, y_start, dd, ds;
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uint8_t *d, *s;
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uint32_t *cptr, *s24;
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if (ts->ds->depth != 32)
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return;
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page = ts->vram_offset;
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page24 = ts->vram24_offset;
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cpage = ts->cplane_offset;
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y_start = -1;
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page_min = 0xffffffff;
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page_max = 0;
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d = ts->ds->data;
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s = ts->vram;
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s24 = ts->vram24;
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cptr = ts->cplane;
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dd = ts->ds->linesize;
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ds = 1024;
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
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if (check_dirty(ts, page, page24, cpage)) {
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if (y_start < 0)
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y_start = y;
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if (page < page_min)
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page_min = page;
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if (page > page_max)
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page_max = page;
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
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d += dd;
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s += ds;
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cptr += ds;
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s24 += ds;
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
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d += dd;
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s += ds;
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cptr += ds;
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s24 += ds;
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
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d += dd;
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s += ds;
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cptr += ds;
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s24 += ds;
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
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d += dd;
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s += ds;
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cptr += ds;
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s24 += ds;
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} else {
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if (y_start >= 0) {
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start);
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y_start = -1;
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}
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d += dd * 4;
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s += ds * 4;
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cptr += ds * 4;
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s24 += ds * 4;
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}
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}
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if (y_start >= 0) {
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start);
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}
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/* reset modified pages */
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if (page_min <= page_max) {
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reset_dirty(ts, page_min, page_max, page24, cpage);
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}
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}
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static void tcx_invalidate_display(void *opaque)
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{
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TCXState *s = opaque;
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@ -211,14 +340,29 @@ static void tcx_invalidate_display(void *opaque)
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}
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}
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static void tcx24_invalidate_display(void *opaque)
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{
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TCXState *s = opaque;
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int i;
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tcx_invalidate_display(s);
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for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
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cpu_physical_memory_set_dirty(s->vram24_offset + i);
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cpu_physical_memory_set_dirty(s->cplane_offset + i);
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}
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}
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static void tcx_save(QEMUFile *f, void *opaque)
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{
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TCXState *s = opaque;
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qemu_put_be32s(f, (uint32_t *)&s->addr);
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qemu_put_be32s(f, (uint32_t *)&s->vram);
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qemu_put_be32s(f, (uint32_t *)&s->vram24);
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qemu_put_be32s(f, (uint32_t *)&s->cplane);
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qemu_put_be16s(f, (uint16_t *)&s->height);
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qemu_put_be16s(f, (uint16_t *)&s->width);
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qemu_put_be16s(f, (uint16_t *)&s->depth);
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qemu_put_buffer(f, s->r, 256);
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qemu_put_buffer(f, s->g, 256);
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qemu_put_buffer(f, s->b, 256);
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@ -230,13 +374,16 @@ static int tcx_load(QEMUFile *f, void *opaque, int version_id)
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{
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TCXState *s = opaque;
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if (version_id != 1)
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if (version_id != 2)
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return -EINVAL;
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qemu_get_be32s(f, (uint32_t *)&s->addr);
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qemu_get_be32s(f, (uint32_t *)&s->vram);
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qemu_get_be32s(f, (uint32_t *)&s->vram24);
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qemu_get_be32s(f, (uint32_t *)&s->cplane);
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qemu_get_be16s(f, (uint16_t *)&s->height);
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qemu_get_be16s(f, (uint16_t *)&s->width);
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qemu_get_be16s(f, (uint16_t *)&s->depth);
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qemu_get_buffer(f, s->r, 256);
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qemu_get_buffer(f, s->g, 256);
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qemu_get_buffer(f, s->b, 256);
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@ -259,8 +406,8 @@ static void tcx_reset(void *opaque)
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s->r[255] = s->g[255] = s->b[255] = 255;
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update_palette_entries(s, 0, 256);
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memset(s->vram, 0, MAXX*MAXY);
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cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY,
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VGA_DIRTY_FLAG);
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cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
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MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
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s->dac_index = 0;
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s->dac_state = 0;
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}
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@ -321,27 +468,54 @@ static CPUWriteMemoryFunc *tcx_dac_write[3] = {
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};
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void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
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unsigned long vram_offset, int vram_size, int width, int height)
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unsigned long vram_offset, int vram_size, int width, int height,
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int depth)
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{
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TCXState *s;
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int io_memory;
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int size;
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s = qemu_mallocz(sizeof(TCXState));
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if (!s)
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return;
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s->ds = ds;
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s->addr = addr;
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s->vram = vram_base;
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s->vram_offset = vram_offset;
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s->width = width;
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s->height = height;
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s->depth = depth;
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// 8-bit plane
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s->vram = vram_base;
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size = vram_size;
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cpu_register_physical_memory(addr + 0x00800000, size, vram_offset);
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vram_offset += size;
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vram_base += size;
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cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
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io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
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cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);
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cpu_register_physical_memory(addr + 0x00200000, TCX_DAC_NREGS, io_memory);
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if (depth == 24) {
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// 24-bit plane
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size = vram_size * 4;
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s->vram24 = (uint32_t *)vram_base;
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s->vram24_offset = vram_offset;
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cpu_register_physical_memory(addr + 0x02000000, size, vram_offset);
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vram_offset += size;
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vram_base += size;
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// Control plane
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size = vram_size * 4;
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s->cplane = (uint32_t *)vram_base;
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s->cplane_offset = vram_offset;
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cpu_register_physical_memory(addr + 0x0a000000, size, vram_offset);
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graphic_console_init(s->ds, tcx24_update_display, tcx24_invalidate_display,
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tcx24_screen_dump, s);
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} else {
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graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
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tcx_screen_dump, s);
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}
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graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
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tcx_screen_dump, s);
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register_savevm("tcx", addr, 1, tcx_save, tcx_load, s);
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qemu_register_reset(tcx_reset, s);
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tcx_reset(s);
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@ -375,5 +549,38 @@ static void tcx_screen_dump(void *opaque, const char *filename)
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return;
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}
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static void tcx24_screen_dump(void *opaque, const char *filename)
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{
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TCXState *s = opaque;
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FILE *f;
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uint8_t *d, *d1, v;
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uint32_t *s24, *cptr, dval;
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int y, x;
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f = fopen(filename, "wb");
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if (!f)
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return;
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fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
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d1 = s->vram;
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s24 = s->vram24;
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cptr = s->cplane;
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for(y = 0; y < s->height; y++) {
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d = d1;
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for(x = 0; x < s->width; x++, d++, s24++) {
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if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
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dval = *s24 & 0x00ffffff;
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fputc((dval >> 16) & 0xff, f);
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fputc((dval >> 8) & 0xff, f);
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fputc(dval & 0xff, f);
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} else {
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v = *d;
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fputc(s->r[v], f);
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fputc(s->g[v], f);
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fputc(s->b[v], f);
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}
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}
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d1 += MAXX;
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}
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fclose(f);
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return;
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}
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3
vl.c
3
vl.c
@ -159,11 +159,12 @@ int vmsvga_enabled = 0;
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#ifdef TARGET_SPARC
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int graphic_width = 1024;
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int graphic_height = 768;
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int graphic_depth = 8;
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#else
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int graphic_width = 800;
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int graphic_height = 600;
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#endif
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int graphic_depth = 15;
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#endif
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int full_screen = 0;
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int no_frame = 0;
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int no_quit = 0;
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7
vl.h
7
vl.h
@ -889,7 +889,11 @@ extern struct soundhw soundhw[];
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/* vga.c */
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#ifndef TARGET_SPARC
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#define VGA_RAM_SIZE (8192 * 1024)
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#else
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#define VGA_RAM_SIZE (9 * 1024 * 1024)
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#endif
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struct DisplayState {
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uint8_t *data;
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@ -1206,7 +1210,8 @@ static inline void sparc_iommu_memory_write(void *opaque,
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/* tcx.c */
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void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
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unsigned long vram_offset, int vram_size, int width, int height);
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unsigned long vram_offset, int vram_size, int width, int height,
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int depth);
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/* slavio_intctl.c */
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void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
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