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target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts

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System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Nicholas Piggin 2023-06-20 23:13:21 +10:00 committed by Cédric Le Goater
parent a3c020d85e
commit eb701f3012
1 changed files with 4 additions and 0 deletions
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4
target/ppc/excp_helper.c
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@ -1591,6 +1591,10 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vhc->hypercall(cpu->vhyp, cpu);
return;
}
if (env->insns_flags2 & PPC2_ISA310) {
/* ISAv3.1 puts LEV into SRR1 */
msr |= lev << 20;
}
if (lev == 1) {
new_msr |= (target_ulong)MSR_HVB;
}