mirror of
https://github.com/qemu/qemu.git
synced 2024-11-25 20:03:37 +08:00
target-arm queue:
* i.MX6UL EVK board: put PHYs in the correct places * hw/arm/virt: Let the virtio-iommu bypass MSIs * target/arm: kvm: Handle DABT with no valid ISS * hw/arm/virt-acpi-build: Only expose flash on older machine types * target/arm: Fix temp double-free in sve ldr/str * hw/display/bcm2835_fb.c: Initialize all fields of struct * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak * Deprecate TileGX port -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl7/YnEZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pmaD/9vE0vEQIz92KoE6haS9oku CigsqHJRp2Q4pYA5Y7omCFR7KnUnmzr6nwDcvEpdq5Pjnp8kV36gNkr1P/KHUAQ3 p9aJ/2jqaQ/BLI/ieIU4kVGzUrF/j+8eLm1+xXGJpl/LG2Ij2NTUwYE+dazcUdRB GsD/c4yRFbJpj/CgPp6tE+sZPy9HrVF4R2K/dUxmbNsYYB5EcY7gxMc+zCpcexFC aoJWOrxlpVBwjrToLpKVxHYG+K0giAaosEocxOJ1Iz0QWVJlBWOr7d8M8Pqoeafp 16tE4PGfEOoHvpFhCu4pidgwKfrRKosG9bm28Bf1Ps2cze9/k2ShdXPRmbcngU32 Ed3PbJ4ZlBoxVvEPLNdcD0aOysGjPUn1wxleFFmlsDfTxfovpF4Ki1OGBFyhb8wk 1m3pi0VyYm6W3rKxl78Hs6Dj3svV4Qdjo8eBePVOgy+KS83Cr1fZX2OSM+4/040M Djxh8uH6tFvpRcFEqf1inQgznT71gTGhiCw4lxZ3OFpOhIJsLSButHcky1HTRCje j3TP5Mcde6NvMKfxJKIU2MSi9pWuPPinkaDBzIgZjNtwG+1bj+jnDX/WJ2LPKFCH aTScz05EaG61TUD3rEsRl6iRRy4dpOV8jqELE8AEir65C33SXZgNuVaRNCacvSaH OZybCU5dKP0TkJH9hNqOKA== =vdip -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200703' into staging target-arm queue: * i.MX6UL EVK board: put PHYs in the correct places * hw/arm/virt: Let the virtio-iommu bypass MSIs * target/arm: kvm: Handle DABT with no valid ISS * hw/arm/virt-acpi-build: Only expose flash on older machine types * target/arm: Fix temp double-free in sve ldr/str * hw/display/bcm2835_fb.c: Initialize all fields of struct * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak * Deprecate TileGX port # gpg: Signature made Fri 03 Jul 2020 17:53:05 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200703: (34 commits) Deprecate TileGX port Replace uses of FROM_SSI_SLAVE() macro with QOM casts hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses hw/arm/spitz: Encapsulate misc GPIO handling in a device hw/misc/max111x: Create header file for documentation, TYPE_ macros hw/misc/max111x: Use GPIO lines rather than max111x_set_input() hw/arm/spitz: Use max111x properties to set initial values ssi: Add ssi_realize_and_unref() hw/misc/max111x: Don't use vmstate_register() hw/misc/max111x: provide QOM properties for setting initial values hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState hw/arm/spitz: Create SpitzMachineClass abstract base class hw/arm/spitz: Detabify hw/display/bcm2835_fb.c: Initialize all fields of struct target/arm: Fix temp double-free in sve ldr/str ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
eb6490f544
@ -787,6 +787,7 @@ F: hw/gpio/max7310.c
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F: hw/gpio/zaurus.c
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F: hw/misc/mst_fpga.c
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F: hw/misc/max111x.c
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F: include/hw/misc/max111x.h
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F: include/hw/arm/pxa.h
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F: include/hw/arm/sharpsl.h
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F: include/hw/display/tc6393xb.h
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@ -404,6 +404,17 @@ The above, converted to the current supported format::
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json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
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linux-user mode CPUs
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--------------------
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``tilegx`` CPUs (since 5.1.0)
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'''''''''''''''''''''''''''''
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The ``tilegx`` guest CPU support (which was only implemented in
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linux-user mode) is deprecated and will be removed in a future version
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of QEMU. Support for this CPU was removed from the upstream Linux
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kernel in 2018, and has also been dropped from glibc.
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Related binaries
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----------------
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|
@ -427,6 +427,9 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
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FSL_IMX6UL_ENET2_TIMER_IRQ,
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};
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object_property_set_uint(OBJECT(&s->eth[i]),
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s->phy_num[i],
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"phy-num", &error_abort);
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object_property_set_uint(OBJECT(&s->eth[i]),
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FSL_IMX6UL_ETH_NUM_TX_RINGS,
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"tx-ring-num", &error_abort);
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@ -607,10 +610,17 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
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FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
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}
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static Property fsl_imx6ul_properties[] = {
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DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
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DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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device_class_set_props(dc, fsl_imx6ul_properties);
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dc->realize = fsl_imx6ul_realize;
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dc->desc = "i.MX6UL SOC";
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/* Reason: Uses serial_hds and nd_table in realize() directly */
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|
@ -40,6 +40,8 @@ static void mcimx6ul_evk_init(MachineState *machine)
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s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
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object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
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object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
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object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
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qdev_realize(DEVICE(s), NULL, &error_fatal);
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memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
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@ -11,6 +11,7 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/arm/pxa.h"
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#include "hw/sysbus.h"
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@ -166,7 +167,9 @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
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case ICHP: /* Highest Priority register */
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return pxa2xx_pic_highest(s);
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default:
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printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
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"\n", offset);
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return 0;
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}
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}
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@ -199,7 +202,9 @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
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s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
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break;
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default:
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printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
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qemu_log_mask(LOG_GUEST_ERROR,
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"pxa2xx_pic_mem_write: bad register offset 0x%"
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HWADDR_PRIx "\n", offset);
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return;
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}
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pxa2xx_pic_update(opaque);
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|
507
hw/arm/spitz.c
507
hw/arm/spitz.c
@ -23,36 +23,66 @@
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#include "hw/ssi/ssi.h"
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#include "hw/block/flash.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "hw/arm/sharpsl.h"
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#include "ui/console.h"
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#include "hw/audio/wm8750.h"
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#include "audio/audio.h"
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/misc/max111x.h"
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#include "migration/vmstate.h"
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#include "exec/address-spaces.h"
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#include "cpu.h"
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#undef REG_FMT
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#define REG_FMT "0x%02lx"
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enum spitz_model_e { spitz, akita, borzoi, terrier };
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typedef struct {
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MachineClass parent;
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enum spitz_model_e model;
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int arm_id;
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} SpitzMachineClass;
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typedef struct {
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MachineState parent;
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PXA2xxState *mpu;
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DeviceState *mux;
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DeviceState *lcdtg;
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DeviceState *ads7846;
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DeviceState *max1111;
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DeviceState *scp0;
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DeviceState *scp1;
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DeviceState *misc_gpio;
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} SpitzMachineState;
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#define TYPE_SPITZ_MACHINE "spitz-common"
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#define SPITZ_MACHINE(obj) \
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OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
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#define SPITZ_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
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#define SPITZ_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
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#define zaurus_printf(format, ...) \
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fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
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/* Spitz Flash */
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#define FLASH_BASE 0x0c000000
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#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
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#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
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#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
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#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
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#define FLASH_ECCCLRR 0x10 /* Clear ECC */
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#define FLASH_FLASHIO 0x14 /* Flash I/O */
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#define FLASH_FLASHCTL 0x18 /* Flash Control */
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#define FLASH_BASE 0x0c000000
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#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
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#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
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#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
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#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
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#define FLASH_ECCCLRR 0x10 /* Clear ECC */
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#define FLASH_FLASHIO 0x14 /* Flash I/O */
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#define FLASH_FLASHCTL 0x18 /* Flash Control */
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||||
|
||||
#define FLASHCTL_CE0 (1 << 0)
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#define FLASHCTL_CLE (1 << 1)
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#define FLASHCTL_ALE (1 << 2)
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#define FLASHCTL_WP (1 << 3)
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#define FLASHCTL_CE1 (1 << 4)
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#define FLASHCTL_RYBY (1 << 5)
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#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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#define FLASHCTL_CE0 (1 << 0)
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#define FLASHCTL_CLE (1 << 1)
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#define FLASHCTL_ALE (1 << 2)
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#define FLASHCTL_WP (1 << 3)
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||||
#define FLASHCTL_CE1 (1 << 4)
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#define FLASHCTL_RYBY (1 << 5)
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#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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#define TYPE_SL_NAND "sl-nand"
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#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
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@ -74,12 +104,12 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
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int ryby;
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||||
|
||||
switch (addr) {
|
||||
#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
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||||
#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
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||||
case FLASH_ECCLPLB:
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return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
|
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BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
|
||||
|
||||
#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
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#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
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case FLASH_ECCLPUB:
|
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return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
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||||
BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
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||||
@ -105,7 +135,9 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
|
||||
return ecc_digest(&s->ecc, nand_getio(s->nand));
|
||||
|
||||
default:
|
||||
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
|
||||
addr);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -136,7 +168,9 @@ static void sl_write(void *opaque, hwaddr addr,
|
||||
break;
|
||||
|
||||
default:
|
||||
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
|
||||
addr);
|
||||
}
|
||||
}
|
||||
|
||||
@ -191,8 +225,8 @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
|
||||
|
||||
/* Spitz Keyboard */
|
||||
|
||||
#define SPITZ_KEY_STROBE_NUM 11
|
||||
#define SPITZ_KEY_SENSE_NUM 7
|
||||
#define SPITZ_KEY_STROBE_NUM 11
|
||||
#define SPITZ_KEY_SENSE_NUM 7
|
||||
|
||||
static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
|
||||
12, 17, 91, 34, 36, 38, 39
|
||||
@ -214,11 +248,11 @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
|
||||
{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
|
||||
};
|
||||
|
||||
#define SPITZ_GPIO_AK_INT 13 /* Remote control */
|
||||
#define SPITZ_GPIO_SYNC 16 /* Sync button */
|
||||
#define SPITZ_GPIO_ON_KEY 95 /* Power button */
|
||||
#define SPITZ_GPIO_SWA 97 /* Lid */
|
||||
#define SPITZ_GPIO_SWB 96 /* Tablet mode */
|
||||
#define SPITZ_GPIO_AK_INT 13 /* Remote control */
|
||||
#define SPITZ_GPIO_SYNC 16 /* Sync button */
|
||||
#define SPITZ_GPIO_ON_KEY 95 /* Power button */
|
||||
#define SPITZ_GPIO_SWA 97 /* Lid */
|
||||
#define SPITZ_GPIO_SWB 96 /* Tablet mode */
|
||||
|
||||
/* The special buttons are mapped to unused keys */
|
||||
static const int spitz_gpiomap[5] = {
|
||||
@ -300,7 +334,7 @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
|
||||
#define SPITZ_MOD_CTRL (1 << 8)
|
||||
#define SPITZ_MOD_FN (1 << 9)
|
||||
|
||||
#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
|
||||
#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
|
||||
|
||||
static void spitz_keyboard_handler(void *opaque, int keycode)
|
||||
{
|
||||
@ -308,25 +342,25 @@ static void spitz_keyboard_handler(void *opaque, int keycode)
|
||||
uint16_t code;
|
||||
int mapcode;
|
||||
switch (keycode) {
|
||||
case 0x2a: /* Left Shift */
|
||||
case 0x2a: /* Left Shift */
|
||||
s->modifiers |= 1;
|
||||
break;
|
||||
case 0xaa:
|
||||
s->modifiers &= ~1;
|
||||
break;
|
||||
case 0x36: /* Right Shift */
|
||||
case 0x36: /* Right Shift */
|
||||
s->modifiers |= 2;
|
||||
break;
|
||||
case 0xb6:
|
||||
s->modifiers &= ~2;
|
||||
break;
|
||||
case 0x1d: /* Control */
|
||||
case 0x1d: /* Control */
|
||||
s->modifiers |= 4;
|
||||
break;
|
||||
case 0x9d:
|
||||
s->modifiers &= ~4;
|
||||
break;
|
||||
case 0x38: /* Alt */
|
||||
case 0x38: /* Alt */
|
||||
s->modifiers |= 8;
|
||||
break;
|
||||
case 0xb8:
|
||||
@ -536,14 +570,17 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
|
||||
|
||||
/* LCD backlight controller */
|
||||
|
||||
#define LCDTG_RESCTL 0x00
|
||||
#define LCDTG_PHACTRL 0x01
|
||||
#define LCDTG_DUTYCTRL 0x02
|
||||
#define LCDTG_POWERREG0 0x03
|
||||
#define LCDTG_POWERREG1 0x04
|
||||
#define LCDTG_GPOR3 0x05
|
||||
#define LCDTG_PICTRL 0x06
|
||||
#define LCDTG_POLCTRL 0x07
|
||||
#define LCDTG_RESCTL 0x00
|
||||
#define LCDTG_PHACTRL 0x01
|
||||
#define LCDTG_DUTYCTRL 0x02
|
||||
#define LCDTG_POWERREG0 0x03
|
||||
#define LCDTG_POWERREG1 0x04
|
||||
#define LCDTG_GPOR3 0x05
|
||||
#define LCDTG_PICTRL 0x06
|
||||
#define LCDTG_POLCTRL 0x07
|
||||
|
||||
#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
|
||||
#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
|
||||
|
||||
typedef struct {
|
||||
SSISlave ssidev;
|
||||
@ -559,12 +596,9 @@ static void spitz_bl_update(SpitzLCDTG *s)
|
||||
zaurus_printf("LCD Backlight now off\n");
|
||||
}
|
||||
|
||||
/* FIXME: Implement GPIO properly and remove this hack. */
|
||||
static SpitzLCDTG *spitz_lcdtg;
|
||||
|
||||
static inline void spitz_bl_bit5(void *opaque, int line, int level)
|
||||
{
|
||||
SpitzLCDTG *s = spitz_lcdtg;
|
||||
SpitzLCDTG *s = opaque;
|
||||
int prev = s->bl_intensity;
|
||||
|
||||
if (level)
|
||||
@ -578,14 +612,14 @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
|
||||
|
||||
static inline void spitz_bl_power(void *opaque, int line, int level)
|
||||
{
|
||||
SpitzLCDTG *s = spitz_lcdtg;
|
||||
SpitzLCDTG *s = opaque;
|
||||
s->bl_power = !!level;
|
||||
spitz_bl_update(s);
|
||||
}
|
||||
|
||||
static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
|
||||
{
|
||||
SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
|
||||
SpitzLCDTG *s = SPITZ_LCDTG(dev);
|
||||
int addr;
|
||||
addr = value >> 5;
|
||||
value &= 0x1f;
|
||||
@ -612,25 +646,29 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
|
||||
static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
|
||||
{
|
||||
SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
|
||||
SpitzLCDTG *s = SPITZ_LCDTG(ssi);
|
||||
DeviceState *dev = DEVICE(s);
|
||||
|
||||
spitz_lcdtg = s;
|
||||
s->bl_power = 0;
|
||||
s->bl_intensity = 0x20;
|
||||
|
||||
qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
|
||||
qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
|
||||
}
|
||||
|
||||
/* SSP devices */
|
||||
|
||||
#define CORGI_SSP_PORT 2
|
||||
#define CORGI_SSP_PORT 2
|
||||
|
||||
#define SPITZ_GPIO_LCDCON_CS 53
|
||||
#define SPITZ_GPIO_ADS7846_CS 14
|
||||
#define SPITZ_GPIO_MAX1111_CS 20
|
||||
#define SPITZ_GPIO_TP_INT 11
|
||||
#define SPITZ_GPIO_LCDCON_CS 53
|
||||
#define SPITZ_GPIO_ADS7846_CS 14
|
||||
#define SPITZ_GPIO_MAX1111_CS 20
|
||||
#define SPITZ_GPIO_TP_INT 11
|
||||
|
||||
static DeviceState *max1111;
|
||||
#define TYPE_CORGI_SSP "corgi-ssp"
|
||||
#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
|
||||
|
||||
/* "Demux" the signal based on current chipselect */
|
||||
typedef struct {
|
||||
@ -641,7 +679,7 @@ typedef struct {
|
||||
|
||||
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
|
||||
{
|
||||
CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
|
||||
CorgiSSPState *s = CORGI_SSP(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
@ -659,29 +697,18 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
|
||||
s->enable[line] = !level;
|
||||
}
|
||||
|
||||
#define MAX1111_BATT_VOLT 1
|
||||
#define MAX1111_BATT_TEMP 2
|
||||
#define MAX1111_ACIN_VOLT 3
|
||||
#define MAX1111_BATT_VOLT 1
|
||||
#define MAX1111_BATT_TEMP 2
|
||||
#define MAX1111_ACIN_VOLT 3
|
||||
|
||||
#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
|
||||
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
|
||||
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
|
||||
|
||||
static void spitz_adc_temp_on(void *opaque, int line, int level)
|
||||
{
|
||||
if (!max1111)
|
||||
return;
|
||||
|
||||
if (level)
|
||||
max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
|
||||
else
|
||||
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
||||
}
|
||||
#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
|
||||
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
|
||||
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
|
||||
|
||||
static void corgi_ssp_realize(SSISlave *d, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(d);
|
||||
CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
|
||||
CorgiSSPState *s = CORGI_SSP(d);
|
||||
|
||||
qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
|
||||
s->bus[0] = ssi_create_bus(dev, "ssi0");
|
||||
@ -689,34 +716,36 @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
|
||||
s->bus[2] = ssi_create_bus(dev, "ssi2");
|
||||
}
|
||||
|
||||
static void spitz_ssp_attach(PXA2xxState *cpu)
|
||||
static void spitz_ssp_attach(SpitzMachineState *sms)
|
||||
{
|
||||
DeviceState *mux;
|
||||
DeviceState *dev;
|
||||
void *bus;
|
||||
|
||||
mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
|
||||
sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
|
||||
TYPE_CORGI_SSP);
|
||||
|
||||
bus = qdev_get_child_bus(mux, "ssi0");
|
||||
ssi_create_slave(bus, "spitz-lcdtg");
|
||||
bus = qdev_get_child_bus(sms->mux, "ssi0");
|
||||
sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
|
||||
|
||||
bus = qdev_get_child_bus(mux, "ssi1");
|
||||
dev = ssi_create_slave(bus, "ads7846");
|
||||
qdev_connect_gpio_out(dev, 0,
|
||||
qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
|
||||
bus = qdev_get_child_bus(sms->mux, "ssi1");
|
||||
sms->ads7846 = ssi_create_slave(bus, "ads7846");
|
||||
qdev_connect_gpio_out(sms->ads7846, 0,
|
||||
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
|
||||
|
||||
bus = qdev_get_child_bus(mux, "ssi2");
|
||||
max1111 = ssi_create_slave(bus, "max1111");
|
||||
max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
|
||||
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
||||
max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
|
||||
bus = qdev_get_child_bus(sms->mux, "ssi2");
|
||||
sms->max1111 = qdev_new(TYPE_MAX_1111);
|
||||
qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
|
||||
SPITZ_BATTERY_VOLT);
|
||||
qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
|
||||
qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
|
||||
SPITZ_CHARGEON_ACIN);
|
||||
ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
|
||||
|
||||
qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
|
||||
qdev_get_gpio_in(mux, 0));
|
||||
qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
|
||||
qdev_get_gpio_in(mux, 1));
|
||||
qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
|
||||
qdev_get_gpio_in(mux, 2));
|
||||
qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
|
||||
qdev_get_gpio_in(sms->mux, 0));
|
||||
qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
|
||||
qdev_get_gpio_in(sms->mux, 1));
|
||||
qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
|
||||
qdev_get_gpio_in(sms->mux, 2));
|
||||
}
|
||||
|
||||
/* CF Microdrive */
|
||||
@ -735,11 +764,11 @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
|
||||
|
||||
/* Wm8750 and Max7310 on I2C */
|
||||
|
||||
#define AKITA_MAX_ADDR 0x18
|
||||
#define SPITZ_WM_ADDRL 0x1b
|
||||
#define SPITZ_WM_ADDRH 0x1a
|
||||
#define AKITA_MAX_ADDR 0x18
|
||||
#define SPITZ_WM_ADDRL 0x1b
|
||||
#define SPITZ_WM_ADDRH 0x1a
|
||||
|
||||
#define SPITZ_GPIO_WM 5
|
||||
#define SPITZ_GPIO_WM 5
|
||||
|
||||
static void spitz_wm8750_addr(void *opaque, int line, int level)
|
||||
{
|
||||
@ -779,75 +808,119 @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
|
||||
|
||||
/* Other peripherals */
|
||||
|
||||
static void spitz_out_switch(void *opaque, int line, int level)
|
||||
/*
|
||||
* Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
|
||||
*
|
||||
* QEMU interface:
|
||||
* + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
|
||||
* these currently just print messages that the line has been signalled
|
||||
* + named GPIO input "adc-temp-on": set to cause the battery-temperature
|
||||
* value to be passed to the max111x ADC
|
||||
* + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
|
||||
*/
|
||||
#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
|
||||
#define SPITZ_MISC_GPIO(obj) \
|
||||
OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
|
||||
|
||||
typedef struct SpitzMiscGPIOState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
qemu_irq adc_value;
|
||||
} SpitzMiscGPIOState;
|
||||
|
||||
static void spitz_misc_charging(void *opaque, int n, int level)
|
||||
{
|
||||
switch (line) {
|
||||
case 0:
|
||||
zaurus_printf("Charging %s.\n", level ? "off" : "on");
|
||||
break;
|
||||
case 1:
|
||||
zaurus_printf("Discharging %s.\n", level ? "on" : "off");
|
||||
break;
|
||||
case 2:
|
||||
zaurus_printf("Green LED %s.\n", level ? "on" : "off");
|
||||
break;
|
||||
case 3:
|
||||
zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
|
||||
break;
|
||||
case 4:
|
||||
spitz_bl_bit5(opaque, line, level);
|
||||
break;
|
||||
case 5:
|
||||
spitz_bl_power(opaque, line, level);
|
||||
break;
|
||||
case 6:
|
||||
spitz_adc_temp_on(opaque, line, level);
|
||||
break;
|
||||
zaurus_printf("Charging %s.\n", level ? "off" : "on");
|
||||
}
|
||||
|
||||
static void spitz_misc_discharging(void *opaque, int n, int level)
|
||||
{
|
||||
zaurus_printf("Discharging %s.\n", level ? "off" : "on");
|
||||
}
|
||||
|
||||
static void spitz_misc_green_led(void *opaque, int n, int level)
|
||||
{
|
||||
zaurus_printf("Green LED %s.\n", level ? "off" : "on");
|
||||
}
|
||||
|
||||
static void spitz_misc_orange_led(void *opaque, int n, int level)
|
||||
{
|
||||
zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
|
||||
}
|
||||
|
||||
static void spitz_misc_adc_temp(void *opaque, int n, int level)
|
||||
{
|
||||
SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
|
||||
int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
|
||||
|
||||
qemu_set_irq(s->adc_value, batt_temp);
|
||||
}
|
||||
|
||||
static void spitz_misc_gpio_init(Object *obj)
|
||||
{
|
||||
SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
|
||||
qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
|
||||
qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
|
||||
qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
|
||||
qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
|
||||
qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
|
||||
|
||||
qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
|
||||
}
|
||||
|
||||
#define SPITZ_SCP_LED_GREEN 1
|
||||
#define SPITZ_SCP_JK_B 2
|
||||
#define SPITZ_SCP_CHRG_ON 3
|
||||
#define SPITZ_SCP_MUTE_L 4
|
||||
#define SPITZ_SCP_MUTE_R 5
|
||||
#define SPITZ_SCP_CF_POWER 6
|
||||
#define SPITZ_SCP_LED_ORANGE 7
|
||||
#define SPITZ_SCP_JK_A 8
|
||||
#define SPITZ_SCP_ADC_TEMP_ON 9
|
||||
#define SPITZ_SCP2_IR_ON 1
|
||||
#define SPITZ_SCP2_AKIN_PULLUP 2
|
||||
#define SPITZ_SCP2_BACKLIGHT_CONT 7
|
||||
#define SPITZ_SCP2_BACKLIGHT_ON 8
|
||||
#define SPITZ_SCP2_MIC_BIAS 9
|
||||
|
||||
static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
|
||||
{
|
||||
DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
|
||||
|
||||
sms->misc_gpio = miscdev;
|
||||
|
||||
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
|
||||
qdev_get_gpio_in_named(miscdev, "charging", 0));
|
||||
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
|
||||
qdev_get_gpio_in_named(miscdev, "discharging", 0));
|
||||
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
|
||||
qdev_get_gpio_in_named(miscdev, "green-led", 0));
|
||||
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
|
||||
qdev_get_gpio_in_named(miscdev, "orange-led", 0));
|
||||
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
|
||||
qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
|
||||
qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
|
||||
qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
|
||||
|
||||
if (sms->scp1) {
|
||||
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
|
||||
qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
|
||||
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
|
||||
qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
|
||||
}
|
||||
}
|
||||
|
||||
#define SPITZ_SCP_LED_GREEN 1
|
||||
#define SPITZ_SCP_JK_B 2
|
||||
#define SPITZ_SCP_CHRG_ON 3
|
||||
#define SPITZ_SCP_MUTE_L 4
|
||||
#define SPITZ_SCP_MUTE_R 5
|
||||
#define SPITZ_SCP_CF_POWER 6
|
||||
#define SPITZ_SCP_LED_ORANGE 7
|
||||
#define SPITZ_SCP_JK_A 8
|
||||
#define SPITZ_SCP_ADC_TEMP_ON 9
|
||||
#define SPITZ_SCP2_IR_ON 1
|
||||
#define SPITZ_SCP2_AKIN_PULLUP 2
|
||||
#define SPITZ_SCP2_BACKLIGHT_CONT 7
|
||||
#define SPITZ_SCP2_BACKLIGHT_ON 8
|
||||
#define SPITZ_SCP2_MIC_BIAS 9
|
||||
|
||||
static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
|
||||
DeviceState *scp0, DeviceState *scp1)
|
||||
{
|
||||
qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
|
||||
|
||||
qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
|
||||
qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
|
||||
qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
|
||||
qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
|
||||
|
||||
if (scp1) {
|
||||
qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
|
||||
qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
|
||||
}
|
||||
|
||||
qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
|
||||
}
|
||||
|
||||
#define SPITZ_GPIO_HSYNC 22
|
||||
#define SPITZ_GPIO_SD_DETECT 9
|
||||
#define SPITZ_GPIO_SD_WP 81
|
||||
#define SPITZ_GPIO_ON_RESET 89
|
||||
#define SPITZ_GPIO_BAT_COVER 90
|
||||
#define SPITZ_GPIO_CF1_IRQ 105
|
||||
#define SPITZ_GPIO_CF1_CD 94
|
||||
#define SPITZ_GPIO_CF2_IRQ 106
|
||||
#define SPITZ_GPIO_CF2_CD 93
|
||||
#define SPITZ_GPIO_HSYNC 22
|
||||
#define SPITZ_GPIO_SD_DETECT 9
|
||||
#define SPITZ_GPIO_SD_WP 81
|
||||
#define SPITZ_GPIO_ON_RESET 89
|
||||
#define SPITZ_GPIO_BAT_COVER 90
|
||||
#define SPITZ_GPIO_CF1_IRQ 105
|
||||
#define SPITZ_GPIO_CF1_CD 94
|
||||
#define SPITZ_GPIO_CF2_IRQ 106
|
||||
#define SPITZ_GPIO_CF2_CD 93
|
||||
|
||||
static int spitz_hsync;
|
||||
|
||||
@ -905,27 +978,27 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
|
||||
}
|
||||
|
||||
/* Board init. */
|
||||
enum spitz_model_e { spitz, akita, borzoi, terrier };
|
||||
|
||||
#define SPITZ_RAM 0x04000000
|
||||
#define SPITZ_ROM 0x00800000
|
||||
#define SPITZ_RAM 0x04000000
|
||||
#define SPITZ_ROM 0x00800000
|
||||
|
||||
static struct arm_boot_info spitz_binfo = {
|
||||
.loader_start = PXA2XX_SDRAM_BASE,
|
||||
.ram_size = 0x04000000,
|
||||
};
|
||||
|
||||
static void spitz_common_init(MachineState *machine,
|
||||
enum spitz_model_e model, int arm_id)
|
||||
static void spitz_common_init(MachineState *machine)
|
||||
{
|
||||
SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
|
||||
SpitzMachineState *sms = SPITZ_MACHINE(machine);
|
||||
enum spitz_model_e model = smc->model;
|
||||
PXA2xxState *mpu;
|
||||
DeviceState *scp0, *scp1 = NULL;
|
||||
MemoryRegion *address_space_mem = get_system_memory();
|
||||
MemoryRegion *rom = g_new(MemoryRegion, 1);
|
||||
|
||||
/* Setup CPU & memory */
|
||||
mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
|
||||
machine->cpu_type);
|
||||
sms->mpu = mpu;
|
||||
|
||||
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
|
||||
|
||||
@ -935,14 +1008,16 @@ static void spitz_common_init(MachineState *machine,
|
||||
/* Setup peripherals */
|
||||
spitz_keyboard_register(mpu);
|
||||
|
||||
spitz_ssp_attach(mpu);
|
||||
spitz_ssp_attach(sms);
|
||||
|
||||
scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
|
||||
sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
|
||||
if (model != akita) {
|
||||
scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
|
||||
sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
|
||||
} else {
|
||||
sms->scp1 = NULL;
|
||||
}
|
||||
|
||||
spitz_scoop_gpio_setup(mpu, scp0, scp1);
|
||||
spitz_scoop_gpio_setup(sms);
|
||||
|
||||
spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
|
||||
|
||||
@ -958,100 +1033,100 @@ static void spitz_common_init(MachineState *machine,
|
||||
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
|
||||
spitz_microdrive_attach(mpu, 0);
|
||||
|
||||
spitz_binfo.board_id = arm_id;
|
||||
spitz_binfo.board_id = smc->arm_id;
|
||||
arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
|
||||
sl_bootparam_write(SL_PXA_PARAM_BASE);
|
||||
}
|
||||
|
||||
static void spitz_init(MachineState *machine)
|
||||
static void spitz_common_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
spitz_common_init(machine, spitz, 0x2c9);
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->block_default_type = IF_IDE;
|
||||
mc->ignore_memory_transaction_failures = true;
|
||||
mc->init = spitz_common_init;
|
||||
}
|
||||
|
||||
static void borzoi_init(MachineState *machine)
|
||||
{
|
||||
spitz_common_init(machine, borzoi, 0x33f);
|
||||
}
|
||||
|
||||
static void akita_init(MachineState *machine)
|
||||
{
|
||||
spitz_common_init(machine, akita, 0x2e8);
|
||||
}
|
||||
|
||||
static void terrier_init(MachineState *machine)
|
||||
{
|
||||
spitz_common_init(machine, terrier, 0x33f);
|
||||
}
|
||||
static const TypeInfo spitz_common_info = {
|
||||
.name = TYPE_SPITZ_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.abstract = true,
|
||||
.instance_size = sizeof(SpitzMachineState),
|
||||
.class_size = sizeof(SpitzMachineClass),
|
||||
.class_init = spitz_common_class_init,
|
||||
};
|
||||
|
||||
static void akitapda_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
|
||||
mc->init = akita_init;
|
||||
mc->ignore_memory_transaction_failures = true;
|
||||
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
|
||||
smc->model = akita;
|
||||
smc->arm_id = 0x2e8;
|
||||
}
|
||||
|
||||
static const TypeInfo akitapda_type = {
|
||||
.name = MACHINE_TYPE_NAME("akita"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.parent = TYPE_SPITZ_MACHINE,
|
||||
.class_init = akitapda_class_init,
|
||||
};
|
||||
|
||||
static void spitzpda_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
|
||||
mc->init = spitz_init;
|
||||
mc->block_default_type = IF_IDE;
|
||||
mc->ignore_memory_transaction_failures = true;
|
||||
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
|
||||
smc->model = spitz;
|
||||
smc->arm_id = 0x2c9;
|
||||
}
|
||||
|
||||
static const TypeInfo spitzpda_type = {
|
||||
.name = MACHINE_TYPE_NAME("spitz"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.parent = TYPE_SPITZ_MACHINE,
|
||||
.class_init = spitzpda_class_init,
|
||||
};
|
||||
|
||||
static void borzoipda_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
|
||||
mc->init = borzoi_init;
|
||||
mc->block_default_type = IF_IDE;
|
||||
mc->ignore_memory_transaction_failures = true;
|
||||
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
|
||||
smc->model = borzoi;
|
||||
smc->arm_id = 0x33f;
|
||||
}
|
||||
|
||||
static const TypeInfo borzoipda_type = {
|
||||
.name = MACHINE_TYPE_NAME("borzoi"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.parent = TYPE_SPITZ_MACHINE,
|
||||
.class_init = borzoipda_class_init,
|
||||
};
|
||||
|
||||
static void terrierpda_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
|
||||
mc->init = terrier_init;
|
||||
mc->block_default_type = IF_IDE;
|
||||
mc->ignore_memory_transaction_failures = true;
|
||||
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
|
||||
smc->model = terrier;
|
||||
smc->arm_id = 0x33f;
|
||||
}
|
||||
|
||||
static const TypeInfo terrierpda_type = {
|
||||
.name = MACHINE_TYPE_NAME("terrier"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.parent = TYPE_SPITZ_MACHINE,
|
||||
.class_init = terrierpda_class_init,
|
||||
};
|
||||
|
||||
static void spitz_machine_init(void)
|
||||
{
|
||||
type_register_static(&spitz_common_info);
|
||||
type_register_static(&akitapda_type);
|
||||
type_register_static(&spitzpda_type);
|
||||
type_register_static(&borzoipda_type);
|
||||
@ -1152,7 +1227,7 @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo corgi_ssp_info = {
|
||||
.name = "corgi-ssp",
|
||||
.name = TYPE_CORGI_SSP,
|
||||
.parent = TYPE_SSI_SLAVE,
|
||||
.instance_size = sizeof(CorgiSSPState),
|
||||
.class_init = corgi_ssp_class_init,
|
||||
@ -1181,18 +1256,30 @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo spitz_lcdtg_info = {
|
||||
.name = "spitz-lcdtg",
|
||||
.name = TYPE_SPITZ_LCDTG,
|
||||
.parent = TYPE_SSI_SLAVE,
|
||||
.instance_size = sizeof(SpitzLCDTG),
|
||||
.class_init = spitz_lcdtg_class_init,
|
||||
};
|
||||
|
||||
static const TypeInfo spitz_misc_gpio_info = {
|
||||
.name = TYPE_SPITZ_MISC_GPIO,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(SpitzMiscGPIOState),
|
||||
.instance_init = spitz_misc_gpio_init,
|
||||
/*
|
||||
* No class_init required: device has no internal state so does not
|
||||
* need to set up reset or vmstate, and does not have a realize method.
|
||||
*/
|
||||
};
|
||||
|
||||
static void spitz_register_types(void)
|
||||
{
|
||||
type_register_static(&corgi_ssp_info);
|
||||
type_register_static(&spitz_lcdtg_info);
|
||||
type_register_static(&spitz_keyboard_info);
|
||||
type_register_static(&sl_nand_info);
|
||||
type_register_static(&spitz_misc_gpio_info);
|
||||
}
|
||||
|
||||
type_init(spitz_register_types)
|
||||
|
@ -749,6 +749,7 @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
|
||||
static void
|
||||
build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
|
||||
{
|
||||
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
|
||||
Aml *scope, *dsdt;
|
||||
MachineState *ms = MACHINE(vms);
|
||||
const MemMapEntry *memmap = vms->memmap;
|
||||
@ -767,7 +768,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
|
||||
acpi_dsdt_add_cpus(scope, vms->smp_cpus);
|
||||
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
|
||||
(irqmap[VIRT_UART] + ARM_SPI_BASE));
|
||||
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
|
||||
if (vmc->acpi_expose_flash) {
|
||||
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
|
||||
}
|
||||
acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
|
||||
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
|
||||
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
|
||||
|
@ -600,6 +600,7 @@ static void create_its(VirtMachineState *vms)
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
|
||||
|
||||
fdt_add_its_gic_node(vms);
|
||||
vms->msi_controller = VIRT_MSI_CTRL_ITS;
|
||||
}
|
||||
|
||||
static void create_v2m(VirtMachineState *vms)
|
||||
@ -620,6 +621,7 @@ static void create_v2m(VirtMachineState *vms)
|
||||
}
|
||||
|
||||
fdt_add_v2m_gic_node(vms);
|
||||
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
|
||||
}
|
||||
|
||||
static void create_gic(VirtMachineState *vms)
|
||||
@ -2198,8 +2200,36 @@ out:
|
||||
static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
|
||||
DeviceState *dev, Error **errp)
|
||||
{
|
||||
VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
|
||||
|
||||
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
|
||||
virt_memory_pre_plug(hotplug_dev, dev, errp);
|
||||
} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
|
||||
hwaddr db_start = 0, db_end = 0;
|
||||
char *resv_prop_str;
|
||||
|
||||
switch (vms->msi_controller) {
|
||||
case VIRT_MSI_CTRL_NONE:
|
||||
return;
|
||||
case VIRT_MSI_CTRL_ITS:
|
||||
/* GITS_TRANSLATER page */
|
||||
db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
|
||||
db_end = base_memmap[VIRT_GIC_ITS].base +
|
||||
base_memmap[VIRT_GIC_ITS].size - 1;
|
||||
break;
|
||||
case VIRT_MSI_CTRL_GICV2M:
|
||||
/* MSI_SETSPI_NS page */
|
||||
db_start = base_memmap[VIRT_GIC_V2M].base;
|
||||
db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
|
||||
break;
|
||||
}
|
||||
resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
|
||||
db_start, db_end,
|
||||
VIRTIO_IOMMU_RESV_MEM_T_MSI);
|
||||
|
||||
qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
|
||||
qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
|
||||
g_free(resv_prop_str);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2480,9 +2510,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
|
||||
|
||||
static void virt_machine_5_0_options(MachineClass *mc)
|
||||
{
|
||||
VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
|
||||
|
||||
virt_machine_5_1_options(mc);
|
||||
compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
|
||||
mc->numa_mem_supported = true;
|
||||
vmc->acpi_expose_flash = true;
|
||||
}
|
||||
DEFINE_VIRT_MACHINE(5, 0)
|
||||
|
||||
|
11
hw/arm/z2.c
11
hw/arm/z2.c
@ -111,9 +111,12 @@ typedef struct {
|
||||
int pos;
|
||||
} ZipitLCD;
|
||||
|
||||
#define TYPE_ZIPIT_LCD "zipit-lcd"
|
||||
#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
|
||||
|
||||
static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
|
||||
{
|
||||
ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
|
||||
ZipitLCD *z = ZIPIT_LCD(dev);
|
||||
uint16_t val;
|
||||
if (z->selected) {
|
||||
z->buf[z->pos] = value & 0xff;
|
||||
@ -153,7 +156,7 @@ static void z2_lcd_cs(void *opaque, int line, int level)
|
||||
|
||||
static void zipit_lcd_realize(SSISlave *dev, Error **errp)
|
||||
{
|
||||
ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
|
||||
ZipitLCD *z = ZIPIT_LCD(dev);
|
||||
z->selected = 0;
|
||||
z->enabled = 0;
|
||||
z->pos = 0;
|
||||
@ -185,7 +188,7 @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo zipit_lcd_info = {
|
||||
.name = "zipit-lcd",
|
||||
.name = TYPE_ZIPIT_LCD,
|
||||
.parent = TYPE_SSI_SLAVE,
|
||||
.instance_size = sizeof(ZipitLCD),
|
||||
.class_init = zipit_lcd_class_init,
|
||||
@ -325,7 +328,7 @@ static void z2_init(MachineState *machine)
|
||||
|
||||
type_register_static(&zipit_lcd_info);
|
||||
type_register_static(&aer915_info);
|
||||
z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
|
||||
z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
|
||||
bus = pxa2xx_i2c_bus(mpu->i2c[0]);
|
||||
i2c_create_slave(bus, TYPE_AER915, 0x55);
|
||||
wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
|
||||
|
@ -15,6 +15,7 @@
|
||||
#include "chardev/char.h"
|
||||
#include "qemu/uuid.h"
|
||||
#include "qemu/units.h"
|
||||
#include "qemu/cutils.h"
|
||||
|
||||
void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
|
||||
Error **errp)
|
||||
@ -578,6 +579,94 @@ const PropertyInfo qdev_prop_macaddr = {
|
||||
.set = set_mac,
|
||||
};
|
||||
|
||||
/* --- Reserved Region --- */
|
||||
|
||||
/*
|
||||
* Accepted syntax:
|
||||
* <low address>:<high address>:<type>
|
||||
* where low/high addresses are uint64_t in hexadecimal
|
||||
* and type is a non-negative decimal integer
|
||||
*/
|
||||
static void get_reserved_region(Object *obj, Visitor *v, const char *name,
|
||||
void *opaque, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
Property *prop = opaque;
|
||||
ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
|
||||
char buffer[64];
|
||||
char *p = buffer;
|
||||
int rc;
|
||||
|
||||
rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
|
||||
rr->low, rr->high, rr->type);
|
||||
assert(rc < sizeof(buffer));
|
||||
|
||||
visit_type_str(v, name, &p, errp);
|
||||
}
|
||||
|
||||
static void set_reserved_region(Object *obj, Visitor *v, const char *name,
|
||||
void *opaque, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
Property *prop = opaque;
|
||||
ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
|
||||
Error *local_err = NULL;
|
||||
const char *endptr;
|
||||
char *str;
|
||||
int ret;
|
||||
|
||||
if (dev->realized) {
|
||||
qdev_prop_set_after_realize(dev, name, errp);
|
||||
return;
|
||||
}
|
||||
|
||||
visit_type_str(v, name, &str, &local_err);
|
||||
if (local_err) {
|
||||
error_propagate(errp, local_err);
|
||||
return;
|
||||
}
|
||||
|
||||
ret = qemu_strtou64(str, &endptr, 16, &rr->low);
|
||||
if (ret) {
|
||||
error_setg(errp, "start address of '%s'"
|
||||
" must be a hexadecimal integer", name);
|
||||
goto out;
|
||||
}
|
||||
if (*endptr != ':') {
|
||||
goto separator_error;
|
||||
}
|
||||
|
||||
ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
|
||||
if (ret) {
|
||||
error_setg(errp, "end address of '%s'"
|
||||
" must be a hexadecimal integer", name);
|
||||
goto out;
|
||||
}
|
||||
if (*endptr != ':') {
|
||||
goto separator_error;
|
||||
}
|
||||
|
||||
ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
|
||||
if (ret) {
|
||||
error_setg(errp, "type of '%s'"
|
||||
" must be a non-negative decimal integer", name);
|
||||
}
|
||||
goto out;
|
||||
|
||||
separator_error:
|
||||
error_setg(errp, "reserved region fields must be separated with ':'");
|
||||
out:
|
||||
g_free(str);
|
||||
return;
|
||||
}
|
||||
|
||||
const PropertyInfo qdev_prop_reserved_region = {
|
||||
.name = "reserved_region",
|
||||
.description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
|
||||
.get = get_reserved_region,
|
||||
.set = set_reserved_region,
|
||||
};
|
||||
|
||||
/* --- on/off/auto --- */
|
||||
|
||||
const PropertyInfo qdev_prop_on_off_auto = {
|
||||
|
@ -29,6 +29,9 @@ typedef struct {
|
||||
int output;
|
||||
} ADS7846State;
|
||||
|
||||
#define TYPE_ADS7846 "ads7846"
|
||||
#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
|
||||
|
||||
/* Control-byte bitfields */
|
||||
#define CB_PD0 (1 << 0)
|
||||
#define CB_PD1 (1 << 1)
|
||||
@ -61,7 +64,7 @@ static void ads7846_int_update(ADS7846State *s)
|
||||
|
||||
static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
|
||||
{
|
||||
ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
|
||||
ADS7846State *s = ADS7846(dev);
|
||||
|
||||
switch (s->cycle ++) {
|
||||
case 0:
|
||||
@ -139,7 +142,7 @@ static const VMStateDescription vmstate_ads7846 = {
|
||||
static void ads7846_realize(SSISlave *d, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(d);
|
||||
ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
|
||||
ADS7846State *s = ADS7846(d);
|
||||
|
||||
qdev_init_gpio_out(dev, &s->interrupt, 1);
|
||||
|
||||
@ -166,7 +169,7 @@ static void ads7846_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo ads7846_info = {
|
||||
.name = "ads7846",
|
||||
.name = TYPE_ADS7846,
|
||||
.parent = TYPE_SSI_SLAVE,
|
||||
.instance_size = sizeof(ADS7846State),
|
||||
.class_init = ads7846_class_init,
|
||||
|
@ -282,6 +282,10 @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
|
||||
newconf.base = s->vcram_base | (value & 0xc0000000);
|
||||
newconf.base += BCM2835_FB_OFFSET;
|
||||
|
||||
/* Copy fields which we don't want to change from the existing config */
|
||||
newconf.pixo = s->config.pixo;
|
||||
newconf.alpha = s->config.alpha;
|
||||
|
||||
bcm2835_fb_validate_config(&newconf);
|
||||
|
||||
pitch = bcm2835_fb_get_pitch(&newconf);
|
||||
|
@ -66,9 +66,13 @@ typedef struct {
|
||||
uint8_t framebuffer[128 * 80 / 2];
|
||||
} ssd0323_state;
|
||||
|
||||
#define TYPE_SSD0323 "ssd0323"
|
||||
#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
|
||||
|
||||
|
||||
static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
|
||||
{
|
||||
ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
|
||||
ssd0323_state *s = SSD0323(dev);
|
||||
|
||||
switch (s->mode) {
|
||||
case SSD0323_DATA:
|
||||
@ -346,7 +350,7 @@ static const GraphicHwOps ssd0323_ops = {
|
||||
static void ssd0323_realize(SSISlave *d, Error **errp)
|
||||
{
|
||||
DeviceState *dev = DEVICE(d);
|
||||
ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
|
||||
ssd0323_state *s = SSD0323(d);
|
||||
|
||||
s->col_end = 63;
|
||||
s->row_end = 79;
|
||||
@ -368,7 +372,7 @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
|
||||
}
|
||||
|
||||
static const TypeInfo ssd0323_info = {
|
||||
.name = "ssd0323",
|
||||
.name = TYPE_SSD0323,
|
||||
.parent = TYPE_SSI_SLAVE,
|
||||
.instance_size = sizeof(ssd0323_state),
|
||||
.class_init = ssd0323_class_init,
|
||||
|
@ -22,9 +22,7 @@
|
||||
#include "hw/sysbus.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qemu/module.h"
|
||||
|
||||
#undef REG_FMT
|
||||
#define REG_FMT "0x%02lx"
|
||||
#include "qemu/log.h"
|
||||
|
||||
/* SCOOP devices */
|
||||
|
||||
@ -104,7 +102,9 @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
|
||||
case SCOOP_GPRR:
|
||||
return s->gpio_level;
|
||||
default:
|
||||
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
|
||||
addr);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -150,7 +150,9 @@ static void scoop_write(void *opaque, hwaddr addr,
|
||||
scoop_gpio_handler_update(s);
|
||||
break;
|
||||
default:
|
||||
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
|
||||
addr);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -11,29 +11,11 @@
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/misc/max111x.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/ssi/ssi.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qemu/module.h"
|
||||
|
||||
typedef struct {
|
||||
SSISlave parent_obj;
|
||||
|
||||
qemu_irq interrupt;
|
||||
uint8_t tb1, rb2, rb3;
|
||||
int cycle;
|
||||
|
||||
uint8_t input[8];
|
||||
int inputs, com;
|
||||
} MAX111xState;
|
||||
|
||||
#define TYPE_MAX_111X "max111x"
|
||||
|
||||
#define MAX_111X(obj) \
|
||||
OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
|
||||
|
||||
#define TYPE_MAX_1110 "max1110"
|
||||
#define TYPE_MAX_1111 "max1111"
|
||||
#include "hw/qdev-properties.h"
|
||||
|
||||
/* Control-byte bitfields */
|
||||
#define CB_PD0 (1 << 0)
|
||||
@ -127,27 +109,24 @@ static const VMStateDescription vmstate_max111x = {
|
||||
}
|
||||
};
|
||||
|
||||
static void max111x_input_set(void *opaque, int line, int value)
|
||||
{
|
||||
MAX111xState *s = MAX_111X(opaque);
|
||||
|
||||
assert(line >= 0 && line < s->inputs);
|
||||
s->input[line] = value;
|
||||
}
|
||||
|
||||
static int max111x_init(SSISlave *d, int inputs)
|
||||
{
|
||||
DeviceState *dev = DEVICE(d);
|
||||
MAX111xState *s = MAX_111X(dev);
|
||||
|
||||
qdev_init_gpio_out(dev, &s->interrupt, 1);
|
||||
qdev_init_gpio_in(dev, max111x_input_set, inputs);
|
||||
|
||||
s->inputs = inputs;
|
||||
/* TODO: add a user interface for setting these */
|
||||
s->input[0] = 0xf0;
|
||||
s->input[1] = 0xe0;
|
||||
s->input[2] = 0xd0;
|
||||
s->input[3] = 0xc0;
|
||||
s->input[4] = 0xb0;
|
||||
s->input[5] = 0xa0;
|
||||
s->input[6] = 0x90;
|
||||
s->input[7] = 0x80;
|
||||
s->com = 0;
|
||||
|
||||
vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
|
||||
&vmstate_max111x, s);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -161,18 +140,51 @@ static void max1111_realize(SSISlave *dev, Error **errp)
|
||||
max111x_init(dev, 4);
|
||||
}
|
||||
|
||||
void max111x_set_input(DeviceState *dev, int line, uint8_t value)
|
||||
static void max111x_reset(DeviceState *dev)
|
||||
{
|
||||
MAX111xState *s = MAX_111X(dev);
|
||||
assert(line >= 0 && line < s->inputs);
|
||||
s->input[line] = value;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < s->inputs; i++) {
|
||||
s->input[i] = s->reset_input[i];
|
||||
}
|
||||
s->com = 0;
|
||||
s->tb1 = 0;
|
||||
s->rb2 = 0;
|
||||
s->rb3 = 0;
|
||||
s->cycle = 0;
|
||||
}
|
||||
|
||||
static Property max1110_properties[] = {
|
||||
/* Reset values for ADC inputs */
|
||||
DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
|
||||
DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
|
||||
DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
|
||||
DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static Property max1111_properties[] = {
|
||||
/* Reset values for ADC inputs */
|
||||
DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
|
||||
DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
|
||||
DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
|
||||
DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
|
||||
DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
|
||||
DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
|
||||
DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
|
||||
DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void max111x_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
k->transfer = max111x_transfer;
|
||||
dc->reset = max111x_reset;
|
||||
dc->vmsd = &vmstate_max111x;
|
||||
}
|
||||
|
||||
static const TypeInfo max111x_info = {
|
||||
@ -186,8 +198,10 @@ static const TypeInfo max111x_info = {
|
||||
static void max1110_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
k->realize = max1110_realize;
|
||||
device_class_set_props(dc, max1110_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo max1110_info = {
|
||||
@ -199,8 +213,10 @@ static const TypeInfo max1110_info = {
|
||||
static void max1111_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
k->realize = max1111_realize;
|
||||
device_class_set_props(dc, max1111_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo max1111_info = {
|
||||
|
@ -280,12 +280,16 @@ static void imx_phy_reset(IMXFECState *s)
|
||||
static uint32_t imx_phy_read(IMXFECState *s, int reg)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t phy = reg / 32;
|
||||
|
||||
if (reg > 31) {
|
||||
/* we only advertise one phy */
|
||||
if (phy != s->phy_num) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
|
||||
TYPE_IMX_FEC, __func__, phy);
|
||||
return 0;
|
||||
}
|
||||
|
||||
reg %= 32;
|
||||
|
||||
switch (reg) {
|
||||
case 0: /* Basic Control */
|
||||
val = s->phy_control;
|
||||
@ -331,20 +335,25 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
|
||||
break;
|
||||
}
|
||||
|
||||
trace_imx_phy_read(val, reg);
|
||||
trace_imx_phy_read(val, phy, reg);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
|
||||
{
|
||||
trace_imx_phy_write(val, reg);
|
||||
uint32_t phy = reg / 32;
|
||||
|
||||
if (reg > 31) {
|
||||
/* we only advertise one phy */
|
||||
if (phy != s->phy_num) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
|
||||
TYPE_IMX_FEC, __func__, phy);
|
||||
return;
|
||||
}
|
||||
|
||||
reg %= 32;
|
||||
|
||||
trace_imx_phy_write(val, phy, reg);
|
||||
|
||||
switch (reg) {
|
||||
case 0: /* Basic Control */
|
||||
if (val & 0x8000) {
|
||||
@ -926,7 +935,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
|
||||
extract32(value,
|
||||
18, 10)));
|
||||
} else {
|
||||
/* This a write operation */
|
||||
/* This is a write operation */
|
||||
imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
|
||||
}
|
||||
/* raise the interrupt as the PHY operation is done */
|
||||
@ -1315,6 +1324,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
|
||||
static Property imx_eth_properties[] = {
|
||||
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
|
||||
DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
|
||||
DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
@ -413,8 +413,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
|
||||
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
|
||||
|
||||
# imx_fec.c
|
||||
imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
|
||||
imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
|
||||
imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
|
||||
imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
|
||||
imx_phy_update_link(const char *s) "%s"
|
||||
imx_phy_reset(void) ""
|
||||
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
|
||||
|
@ -74,7 +74,7 @@ typedef struct {
|
||||
|
||||
static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
|
||||
{
|
||||
ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
|
||||
ssi_sd_state *s = SSI_SD(dev);
|
||||
|
||||
/* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */
|
||||
if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
|
||||
@ -241,7 +241,7 @@ static const VMStateDescription vmstate_ssi_sd = {
|
||||
|
||||
static void ssi_sd_realize(SSISlave *d, Error **errp)
|
||||
{
|
||||
ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
|
||||
ssi_sd_state *s = SSI_SD(d);
|
||||
DeviceState *carddev;
|
||||
DriveInfo *dinfo;
|
||||
Error *err = NULL;
|
||||
|
@ -90,11 +90,16 @@ static const TypeInfo ssi_slave_info = {
|
||||
.abstract = true,
|
||||
};
|
||||
|
||||
bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
|
||||
{
|
||||
return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
|
||||
}
|
||||
|
||||
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
|
||||
{
|
||||
DeviceState *dev = qdev_new(name);
|
||||
|
||||
qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
|
||||
ssi_realize_and_unref(dev, bus, &error_fatal);
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
@ -74,3 +74,4 @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
|
||||
virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
|
||||
virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
|
||||
virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
|
||||
virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
|
||||
|
@ -33,6 +33,9 @@ struct VirtIOIOMMUPCI {
|
||||
|
||||
static Property virtio_iommu_pci_properties[] = {
|
||||
DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
|
||||
DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
|
||||
vdev.nb_reserved_regions, vdev.reserved_regions,
|
||||
qdev_prop_reserved_region, ReservedRegion),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
@ -40,6 +43,7 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
|
||||
{
|
||||
VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
|
||||
DeviceState *vdev = DEVICE(&dev->vdev);
|
||||
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
|
||||
|
||||
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
|
||||
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
|
||||
@ -54,6 +58,13 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
|
||||
"-no-acpi\n");
|
||||
return;
|
||||
}
|
||||
for (int i = 0; i < s->nb_reserved_regions; i++) {
|
||||
if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
|
||||
s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
|
||||
error_setg(errp, "reserved region %d has an invalid type", i);
|
||||
error_append_hint(errp, "Valid values are 0 and 1\n");
|
||||
}
|
||||
}
|
||||
object_property_set_link(OBJECT(dev),
|
||||
OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
|
||||
"primary-bus", &error_abort);
|
||||
|
@ -38,6 +38,7 @@
|
||||
|
||||
/* Max size */
|
||||
#define VIOMMU_DEFAULT_QUEUE_SIZE 256
|
||||
#define VIOMMU_PROBE_SIZE 512
|
||||
|
||||
typedef struct VirtIOIOMMUDomain {
|
||||
uint32_t id;
|
||||
@ -378,6 +379,65 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
|
||||
uint8_t *buf, size_t free)
|
||||
{
|
||||
struct virtio_iommu_probe_resv_mem prop = {};
|
||||
size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
|
||||
int i;
|
||||
|
||||
total = size * s->nb_reserved_regions;
|
||||
|
||||
if (total > free) {
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
for (i = 0; i < s->nb_reserved_regions; i++) {
|
||||
unsigned subtype = s->reserved_regions[i].type;
|
||||
|
||||
assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
|
||||
subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
|
||||
prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
|
||||
prop.head.length = cpu_to_le16(length);
|
||||
prop.subtype = subtype;
|
||||
prop.start = cpu_to_le64(s->reserved_regions[i].low);
|
||||
prop.end = cpu_to_le64(s->reserved_regions[i].high);
|
||||
|
||||
memcpy(buf, &prop, size);
|
||||
|
||||
trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
|
||||
prop.start, prop.end);
|
||||
buf += size;
|
||||
}
|
||||
return total;
|
||||
}
|
||||
|
||||
/**
|
||||
* virtio_iommu_probe - Fill the probe request buffer with
|
||||
* the properties the device is able to return
|
||||
*/
|
||||
static int virtio_iommu_probe(VirtIOIOMMU *s,
|
||||
struct virtio_iommu_req_probe *req,
|
||||
uint8_t *buf)
|
||||
{
|
||||
uint32_t ep_id = le32_to_cpu(req->endpoint);
|
||||
size_t free = VIOMMU_PROBE_SIZE;
|
||||
ssize_t count;
|
||||
|
||||
if (!virtio_iommu_mr(s, ep_id)) {
|
||||
return VIRTIO_IOMMU_S_NOENT;
|
||||
}
|
||||
|
||||
count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
|
||||
if (count < 0) {
|
||||
return VIRTIO_IOMMU_S_INVAL;
|
||||
}
|
||||
buf += count;
|
||||
free -= count;
|
||||
|
||||
return VIRTIO_IOMMU_S_OK;
|
||||
}
|
||||
|
||||
static int virtio_iommu_iov_to_req(struct iovec *iov,
|
||||
unsigned int iov_cnt,
|
||||
void *req, size_t req_sz)
|
||||
@ -407,15 +467,27 @@ virtio_iommu_handle_req(detach)
|
||||
virtio_iommu_handle_req(map)
|
||||
virtio_iommu_handle_req(unmap)
|
||||
|
||||
static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
|
||||
struct iovec *iov,
|
||||
unsigned int iov_cnt,
|
||||
uint8_t *buf)
|
||||
{
|
||||
struct virtio_iommu_req_probe req;
|
||||
int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
|
||||
|
||||
return ret ? ret : virtio_iommu_probe(s, &req, buf);
|
||||
}
|
||||
|
||||
static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
|
||||
{
|
||||
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
|
||||
struct virtio_iommu_req_head head;
|
||||
struct virtio_iommu_req_tail tail = {};
|
||||
size_t output_size = sizeof(tail), sz;
|
||||
VirtQueueElement *elem;
|
||||
unsigned int iov_cnt;
|
||||
struct iovec *iov;
|
||||
size_t sz;
|
||||
void *buf = NULL;
|
||||
|
||||
for (;;) {
|
||||
elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
|
||||
@ -452,6 +524,17 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
|
||||
case VIRTIO_IOMMU_T_UNMAP:
|
||||
tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
|
||||
break;
|
||||
case VIRTIO_IOMMU_T_PROBE:
|
||||
{
|
||||
struct virtio_iommu_req_tail *ptail;
|
||||
|
||||
output_size = s->config.probe_size + sizeof(tail);
|
||||
buf = g_malloc0(output_size);
|
||||
|
||||
ptail = (struct virtio_iommu_req_tail *)
|
||||
(buf + s->config.probe_size);
|
||||
ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
|
||||
}
|
||||
default:
|
||||
tail.status = VIRTIO_IOMMU_S_UNSUPP;
|
||||
}
|
||||
@ -459,12 +542,13 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
|
||||
|
||||
out:
|
||||
sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
|
||||
&tail, sizeof(tail));
|
||||
assert(sz == sizeof(tail));
|
||||
buf ? buf : &tail, output_size);
|
||||
assert(sz == output_size);
|
||||
|
||||
virtqueue_push(vq, elem, sizeof(tail));
|
||||
virtqueue_push(vq, elem, sz);
|
||||
virtio_notify(vdev, vq);
|
||||
g_free(elem);
|
||||
g_free(buf);
|
||||
}
|
||||
}
|
||||
|
||||
@ -523,6 +607,7 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
|
||||
uint32_t sid, flags;
|
||||
bool bypass_allowed;
|
||||
bool found;
|
||||
int i;
|
||||
|
||||
interval.low = addr;
|
||||
interval.high = addr + 1;
|
||||
@ -556,6 +641,25 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
for (i = 0; i < s->nb_reserved_regions; i++) {
|
||||
ReservedRegion *reg = &s->reserved_regions[i];
|
||||
|
||||
if (addr >= reg->low && addr <= reg->high) {
|
||||
switch (reg->type) {
|
||||
case VIRTIO_IOMMU_RESV_MEM_T_MSI:
|
||||
entry.perm = flag;
|
||||
break;
|
||||
case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
|
||||
default:
|
||||
virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
|
||||
VIRTIO_IOMMU_FAULT_F_ADDRESS,
|
||||
sid, addr);
|
||||
break;
|
||||
}
|
||||
goto unlock;
|
||||
}
|
||||
}
|
||||
|
||||
if (!ep->domain) {
|
||||
if (!bypass_allowed) {
|
||||
error_report_once("%s %02x:%02x.%01x not attached to any domain",
|
||||
@ -667,6 +771,7 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
|
||||
s->config.page_size_mask = TARGET_PAGE_MASK;
|
||||
s->config.input_range.end = -1UL;
|
||||
s->config.domain_range.end = 32;
|
||||
s->config.probe_size = VIOMMU_PROBE_SIZE;
|
||||
|
||||
virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
|
||||
virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
|
||||
@ -676,6 +781,7 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
|
||||
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
|
||||
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
|
||||
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
|
||||
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
|
||||
|
||||
qemu_mutex_init(&s->mutex);
|
||||
|
||||
|
@ -51,6 +51,12 @@ extern bool global_dirty_log;
|
||||
|
||||
typedef struct MemoryRegionOps MemoryRegionOps;
|
||||
|
||||
struct ReservedRegion {
|
||||
hwaddr low;
|
||||
hwaddr high;
|
||||
unsigned type;
|
||||
};
|
||||
|
||||
typedef struct IOMMUTLBEntry IOMMUTLBEntry;
|
||||
|
||||
/* See address_space_translate: bit 0 is read, bit 1 is write. */
|
||||
|
@ -87,6 +87,8 @@ typedef struct FslIMX6ULState {
|
||||
MemoryRegion caam;
|
||||
MemoryRegion ocram;
|
||||
MemoryRegion ocram_alias;
|
||||
|
||||
uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
|
||||
} FslIMX6ULState;
|
||||
|
||||
enum FslIMX6ULMemoryMap {
|
||||
|
@ -184,7 +184,6 @@ struct PXA2xxI2SState {
|
||||
};
|
||||
|
||||
# define PA_FMT "0x%08lx"
|
||||
# define REG_FMT "0x" TARGET_FMT_plx
|
||||
|
||||
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
|
||||
const char *revision);
|
||||
|
@ -9,9 +9,6 @@
|
||||
|
||||
#include "exec/hwaddr.h"
|
||||
|
||||
#define zaurus_printf(format, ...) \
|
||||
fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
|
||||
|
||||
/* zaurus.c */
|
||||
|
||||
#define SL_PXA_PARAM_BASE 0xa0000a00
|
||||
|
@ -96,6 +96,12 @@ typedef enum VirtIOMMUType {
|
||||
VIRT_IOMMU_VIRTIO,
|
||||
} VirtIOMMUType;
|
||||
|
||||
typedef enum VirtMSIControllerType {
|
||||
VIRT_MSI_CTRL_NONE,
|
||||
VIRT_MSI_CTRL_GICV2M,
|
||||
VIRT_MSI_CTRL_ITS,
|
||||
} VirtMSIControllerType;
|
||||
|
||||
typedef enum VirtGICType {
|
||||
VIRT_GIC_VERSION_MAX,
|
||||
VIRT_GIC_VERSION_HOST,
|
||||
@ -119,6 +125,7 @@ typedef struct {
|
||||
bool no_highmem_ecam;
|
||||
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
|
||||
bool kvm_no_adjvtime;
|
||||
bool acpi_expose_flash;
|
||||
} VirtMachineClass;
|
||||
|
||||
typedef struct {
|
||||
@ -136,6 +143,7 @@ typedef struct {
|
||||
OnOffAuto acpi;
|
||||
VirtGICType gic_version;
|
||||
VirtIOMMUType iommu;
|
||||
VirtMSIControllerType msi_controller;
|
||||
uint16_t virtio_iommu_bdf;
|
||||
struct arm_boot_info bootinfo;
|
||||
MemMapEntry *memmap;
|
||||
|
56
include/hw/misc/max111x.h
Normal file
56
include/hw/misc/max111x.h
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Maxim MAX1110/1111 ADC chip emulation.
|
||||
*
|
||||
* Copyright (c) 2006 Openedhand Ltd.
|
||||
* Written by Andrzej Zaborowski <balrog@zabor.org>
|
||||
*
|
||||
* This code is licensed under the GNU GPLv2.
|
||||
*
|
||||
* Contributions after 2012-01-13 are licensed under the terms of the
|
||||
* GNU GPL, version 2 or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef HW_MISC_MAX111X_H
|
||||
#define HW_MISC_MAX111X_H
|
||||
|
||||
#include "hw/ssi/ssi.h"
|
||||
|
||||
/*
|
||||
* This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
|
||||
* is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
|
||||
* 8-bit ADC channels.
|
||||
*
|
||||
* QEMU interface:
|
||||
* + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
|
||||
* of each ADC input, as an unsigned 8-bit value
|
||||
* + GPIO output 0: interrupt line
|
||||
* + Properties "input0" to "input3" (max1110) or "input0" to "input7"
|
||||
* (max1111): initial reset values for ADC inputs.
|
||||
*
|
||||
* Known bugs:
|
||||
* + the interrupt line is not correctly implemented, and will never
|
||||
* be lowered once it has been asserted.
|
||||
*/
|
||||
typedef struct {
|
||||
SSISlave parent_obj;
|
||||
|
||||
qemu_irq interrupt;
|
||||
/* Values of inputs at system reset (settable by QOM property) */
|
||||
uint8_t reset_input[8];
|
||||
|
||||
uint8_t tb1, rb2, rb3;
|
||||
int cycle;
|
||||
|
||||
uint8_t input[8];
|
||||
int inputs, com;
|
||||
} MAX111xState;
|
||||
|
||||
#define TYPE_MAX_111X "max111x"
|
||||
|
||||
#define MAX_111X(obj) \
|
||||
OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
|
||||
|
||||
#define TYPE_MAX_1110 "max1110"
|
||||
#define TYPE_MAX_1111 "max1111"
|
||||
|
||||
#endif
|
@ -268,6 +268,7 @@ typedef struct IMXFECState {
|
||||
uint32_t phy_advertise;
|
||||
uint32_t phy_int;
|
||||
uint32_t phy_int_mask;
|
||||
uint32_t phy_num;
|
||||
|
||||
bool is_fec;
|
||||
|
||||
|
@ -19,6 +19,7 @@ extern const PropertyInfo qdev_prop_string;
|
||||
extern const PropertyInfo qdev_prop_chr;
|
||||
extern const PropertyInfo qdev_prop_tpm;
|
||||
extern const PropertyInfo qdev_prop_macaddr;
|
||||
extern const PropertyInfo qdev_prop_reserved_region;
|
||||
extern const PropertyInfo qdev_prop_on_off_auto;
|
||||
extern const PropertyInfo qdev_prop_multifd_compression;
|
||||
extern const PropertyInfo qdev_prop_losttickpolicy;
|
||||
@ -184,6 +185,8 @@ extern const PropertyInfo qdev_prop_pcie_link_width;
|
||||
DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
|
||||
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
|
||||
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
|
||||
#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f) \
|
||||
DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
|
||||
#define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
|
||||
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
|
||||
#define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
|
||||
|
@ -66,8 +66,6 @@ struct SSISlave {
|
||||
bool cs;
|
||||
};
|
||||
|
||||
#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
|
||||
|
||||
extern const VMStateDescription vmstate_ssi_slave;
|
||||
|
||||
#define VMSTATE_SSI_SLAVE(_field, _state) { \
|
||||
@ -79,13 +77,36 @@ extern const VMStateDescription vmstate_ssi_slave;
|
||||
}
|
||||
|
||||
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
|
||||
/**
|
||||
* ssi_realize_and_unref: realize and unref an SSI slave device
|
||||
* @dev: SSI slave device to realize
|
||||
* @bus: SSI bus to put it on
|
||||
* @errp: error pointer
|
||||
*
|
||||
* Call 'realize' on @dev, put it on the specified @bus, and drop the
|
||||
* reference to it. Errors are reported via @errp and by returning
|
||||
* false.
|
||||
*
|
||||
* This function is useful if you have created @dev via qdev_new()
|
||||
* (which takes a reference to the device it returns to you), so that
|
||||
* you can set properties on it before realizing it. If you don't need
|
||||
* to set properties then ssi_create_slave() is probably better (as it
|
||||
* does the create, init and realize in one step).
|
||||
*
|
||||
* If you are embedding the SSI slave into another QOM device and
|
||||
* initialized it via some variant on object_initialize_child() then
|
||||
* do not use this function, because that family of functions arrange
|
||||
* for the only reference to the child device to be held by the parent
|
||||
* via the child<> property, and so the reference-count-drop done here
|
||||
* would be incorrect. (Instead you would want ssi_realize(), which
|
||||
* doesn't currently exist but would be trivial to create if we had
|
||||
* any code that wanted it.)
|
||||
*/
|
||||
bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
|
||||
|
||||
/* Master interface. */
|
||||
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
|
||||
|
||||
uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
|
||||
|
||||
/* max111x.c */
|
||||
void max111x_set_input(DeviceState *dev, int line, uint8_t value);
|
||||
|
||||
#endif
|
||||
|
@ -53,6 +53,8 @@ typedef struct VirtIOIOMMU {
|
||||
GHashTable *as_by_busptr;
|
||||
IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
|
||||
PCIBus *primary_bus;
|
||||
ReservedRegion *reserved_regions;
|
||||
uint32_t nb_reserved_regions;
|
||||
GTree *domains;
|
||||
QemuMutex mutex;
|
||||
GTree *endpoints;
|
||||
|
@ -58,6 +58,7 @@ typedef struct ISABus ISABus;
|
||||
typedef struct ISADevice ISADevice;
|
||||
typedef struct IsaDma IsaDma;
|
||||
typedef struct MACAddr MACAddr;
|
||||
typedef struct ReservedRegion ReservedRegion;
|
||||
typedef struct MachineClass MachineClass;
|
||||
typedef struct MachineState MachineState;
|
||||
typedef struct MemoryListener MemoryListener;
|
||||
|
@ -573,6 +573,8 @@ typedef struct CPUARMState {
|
||||
uint64_t esr;
|
||||
} serror;
|
||||
|
||||
uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
|
||||
|
||||
/* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
|
||||
uint32_t irq_line_state;
|
||||
|
||||
|
@ -39,6 +39,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
|
||||
|
||||
static bool cap_has_mp_state;
|
||||
static bool cap_has_inject_serror_esr;
|
||||
static bool cap_has_inject_ext_dabt;
|
||||
|
||||
static ARMHostCPUFeatures arm_host_cpu_features;
|
||||
|
||||
@ -245,6 +246,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
|
||||
if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
|
||||
error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
|
||||
} else {
|
||||
/* Set status for supporting the external dabt injection */
|
||||
cap_has_inject_ext_dabt = kvm_check_extension(s,
|
||||
KVM_CAP_ARM_INJECT_EXT_DABT);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -738,6 +749,29 @@ int kvm_get_vcpu_events(ARMCPU *cpu)
|
||||
|
||||
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
|
||||
if (unlikely(env->ext_dabt_raised)) {
|
||||
/*
|
||||
* Verifying that the ext DABT has been properly injected,
|
||||
* otherwise risking indefinitely re-running the faulting instruction
|
||||
* Covering a very narrow case for kernels 5.5..5.5.4
|
||||
* when injected abort was misconfigured to be
|
||||
* an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
|
||||
*/
|
||||
if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
|
||||
unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
|
||||
|
||||
error_report("Data abort exception with no valid ISS generated by "
|
||||
"guest memory access. KVM unable to emulate faulting "
|
||||
"instruction. Failed to inject an external data abort "
|
||||
"into the guest.");
|
||||
abort();
|
||||
}
|
||||
/* Clear the status */
|
||||
env->ext_dabt_raised = 0;
|
||||
}
|
||||
}
|
||||
|
||||
MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
|
||||
@ -810,6 +844,47 @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_arm_handle_dabt_nisv:
|
||||
* @cs: CPUState
|
||||
* @esr_iss: ISS encoding (limited) for the exception from Data Abort
|
||||
* ISV bit set to '0b0' -> no valid instruction syndrome
|
||||
* @fault_ipa: faulting address for the synchronous data abort
|
||||
*
|
||||
* Returns: 0 if the exception has been handled, < 0 otherwise
|
||||
*/
|
||||
static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
|
||||
uint64_t fault_ipa)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
/*
|
||||
* Request KVM to inject the external data abort into the guest
|
||||
*/
|
||||
if (cap_has_inject_ext_dabt) {
|
||||
struct kvm_vcpu_events events = { };
|
||||
/*
|
||||
* The external data abort event will be handled immediately by KVM
|
||||
* using the address fault that triggered the exit on given VCPU.
|
||||
* Requesting injection of the external data abort does not rely
|
||||
* on any other VCPU state. Therefore, in this particular case, the VCPU
|
||||
* synchronization can be exceptionally skipped.
|
||||
*/
|
||||
events.exception.ext_dabt_pending = 1;
|
||||
/* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
|
||||
if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
|
||||
env->ext_dabt_raised = 1;
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
error_report("Data abort exception triggered by guest memory access "
|
||||
"at physical address: 0x" TARGET_FMT_lx,
|
||||
(target_ulong)fault_ipa);
|
||||
error_printf("KVM unable to emulate faulting instruction.\n");
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
|
||||
{
|
||||
int ret = 0;
|
||||
@ -820,6 +895,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
|
||||
ret = EXCP_DEBUG;
|
||||
} /* otherwise return to guest */
|
||||
break;
|
||||
case KVM_EXIT_ARM_NISV:
|
||||
/* External DABT with no valid iss to decode */
|
||||
ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
|
||||
run->arm_nisv.fault_ipa);
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
|
||||
__func__, run->exit_reason);
|
||||
|
@ -559,3 +559,37 @@ void kvm_arm_pmu_init(CPUState *cs)
|
||||
{
|
||||
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
|
||||
}
|
||||
|
||||
#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0)
|
||||
#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
|
||||
/*
|
||||
*DFSR:
|
||||
* TTBCR.EAE == 0
|
||||
* FS[4] - DFSR[10]
|
||||
* FS[3:0] - DFSR[3:0]
|
||||
* TTBCR.EAE == 1
|
||||
* FS, bits [5:0]
|
||||
*/
|
||||
#define DFSR_FSC(lpae, v) \
|
||||
((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
|
||||
|
||||
#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
|
||||
|
||||
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
|
||||
{
|
||||
uint32_t dfsr_val;
|
||||
|
||||
if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
uint32_t ttbcr;
|
||||
int lpae = 0;
|
||||
|
||||
if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
|
||||
lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
|
||||
}
|
||||
/* The verification is based on FS filed of the DFSR reg only*/
|
||||
return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
@ -1493,3 +1493,52 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
|
||||
#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
|
||||
|
||||
/*
|
||||
* ESR_EL1
|
||||
* ISS encoding
|
||||
* AARCH64: DFSC, bits [5:0]
|
||||
* AARCH32:
|
||||
* TTBCR.EAE == 0
|
||||
* FS[4] - DFSR[10]
|
||||
* FS[3:0] - DFSR[3:0]
|
||||
* TTBCR.EAE == 1
|
||||
* FS, bits [5:0]
|
||||
*/
|
||||
#define ESR_DFSC(aarch64, lpae, v) \
|
||||
((aarch64 || (lpae)) ? ((v) & 0x3F) \
|
||||
: (((v) >> 6) | ((v) & 0x1F)))
|
||||
|
||||
#define ESR_DFSC_EXTABT(aarch64, lpae) \
|
||||
((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
|
||||
|
||||
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
|
||||
{
|
||||
uint64_t dfsr_val;
|
||||
|
||||
if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
CPUARMState *env = &cpu->env;
|
||||
int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
|
||||
int lpae = 0;
|
||||
|
||||
if (!aarch64_mode) {
|
||||
uint64_t ttbcr;
|
||||
|
||||
if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
|
||||
lpae = arm_feature(env, ARM_FEATURE_LPAE)
|
||||
&& (ttbcr & TTBCR_EAE);
|
||||
}
|
||||
}
|
||||
/*
|
||||
* The verification here is based on the DFSC bits
|
||||
* of the ESR_EL1 reg only
|
||||
*/
|
||||
return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
|
||||
ESR_DFSC_EXTABT(aarch64_mode, lpae));
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
@ -449,6 +449,16 @@ bool kvm_arm_hw_debug_active(CPUState *cs);
|
||||
struct kvm_guest_debug_arch;
|
||||
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
|
||||
|
||||
/**
|
||||
* kvm_arm_verify_ext_dabt_pending:
|
||||
* @cs: CPUState
|
||||
*
|
||||
* Verify the fault status code wrt the Ext DABT injection
|
||||
*
|
||||
* Returns: true if the fault status code is as expected, false otherwise
|
||||
*/
|
||||
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
|
||||
|
||||
/**
|
||||
* its_class_name:
|
||||
*
|
||||
|
@ -461,6 +461,12 @@ TCGv_i64 new_tmp_a64(DisasContext *s)
|
||||
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
|
||||
}
|
||||
|
||||
TCGv_i64 new_tmp_a64_local(DisasContext *s)
|
||||
{
|
||||
assert(s->tmp_a64_count < TMP_A64_MAX);
|
||||
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
|
||||
}
|
||||
|
||||
TCGv_i64 new_tmp_a64_zero(DisasContext *s)
|
||||
{
|
||||
TCGv_i64 t = new_tmp_a64(s);
|
||||
|
@ -30,6 +30,7 @@ void unallocated_encoding(DisasContext *s);
|
||||
} while (0)
|
||||
|
||||
TCGv_i64 new_tmp_a64(DisasContext *s);
|
||||
TCGv_i64 new_tmp_a64_local(DisasContext *s);
|
||||
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
|
||||
TCGv_i64 cpu_reg(DisasContext *s, int reg);
|
||||
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
|
||||
|
@ -4372,9 +4372,8 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
|
||||
|
||||
/* Copy the clean address into a local temp, live across the loop. */
|
||||
t0 = clean_addr;
|
||||
clean_addr = tcg_temp_local_new_i64();
|
||||
clean_addr = new_tmp_a64_local(s);
|
||||
tcg_gen_mov_i64(clean_addr, t0);
|
||||
tcg_temp_free_i64(t0);
|
||||
|
||||
gen_set_label(loop);
|
||||
|
||||
@ -4422,7 +4421,6 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
|
||||
tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
tcg_temp_free_i64(clean_addr);
|
||||
}
|
||||
|
||||
/* Similarly for stores. */
|
||||
@ -4463,9 +4461,8 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
|
||||
|
||||
/* Copy the clean address into a local temp, live across the loop. */
|
||||
t0 = clean_addr;
|
||||
clean_addr = tcg_temp_local_new_i64();
|
||||
clean_addr = new_tmp_a64_local(s);
|
||||
tcg_gen_mov_i64(clean_addr, t0);
|
||||
tcg_temp_free_i64(t0);
|
||||
|
||||
gen_set_label(loop);
|
||||
|
||||
@ -4509,7 +4506,6 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
|
||||
}
|
||||
tcg_temp_free_i64(t0);
|
||||
}
|
||||
tcg_temp_free_i64(clean_addr);
|
||||
}
|
||||
|
||||
static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
|
||||
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,19 +1 @@
|
||||
/* List of comma-separated changed AML files to ignore */
|
||||
"tests/data/acpi/pc/DSDT",
|
||||
"tests/data/acpi/pc/DSDT.acpihmat",
|
||||
"tests/data/acpi/pc/DSDT.bridge",
|
||||
"tests/data/acpi/pc/DSDT.cphp",
|
||||
"tests/data/acpi/pc/DSDT.dimmpxm",
|
||||
"tests/data/acpi/pc/DSDT.ipmikcs",
|
||||
"tests/data/acpi/pc/DSDT.memhp",
|
||||
"tests/data/acpi/pc/DSDT.numamem",
|
||||
"tests/data/acpi/q35/DSDT",
|
||||
"tests/data/acpi/q35/DSDT.acpihmat",
|
||||
"tests/data/acpi/q35/DSDT.bridge",
|
||||
"tests/data/acpi/q35/DSDT.cphp",
|
||||
"tests/data/acpi/q35/DSDT.dimmpxm",
|
||||
"tests/data/acpi/q35/DSDT.ipmibt",
|
||||
"tests/data/acpi/q35/DSDT.memhp",
|
||||
"tests/data/acpi/q35/DSDT.mmio64",
|
||||
"tests/data/acpi/q35/DSDT.numamem",
|
||||
"tests/data/acpi/q35/DSDT.tis",
|
||||
|
Loading…
Reference in New Issue
Block a user