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target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational register, and 1 control register). There is also a zero register, but it does not have any corresponding variable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -170,6 +170,16 @@ struct TCState {
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MSACSR_FS_MASK)
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float_status msa_fp_status;
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#define NUMBER_OF_MXU_REGISTERS 16
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target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
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target_ulong mxu_cr;
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#define MXU_CR_LC 31
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#define MXU_CR_RC 30
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#define MXU_CR_BIAS 2
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#define MXU_CR_RD_EN 1
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#define MXU_CR_MXU_EN 0
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};
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typedef struct CPUMIPSState CPUMIPSState;
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@ -2379,6 +2379,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
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static TCGv_i64 fpu_f64[32];
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static TCGv_i64 msa_wr_d[64];
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/* MXU registers */
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static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
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static TCGv mxu_CR;
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#include "exec/gen-icount.h"
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#define gen_helper_0e0i(name, arg) do { \
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@ -2501,6 +2505,11 @@ static const char * const msaregnames[] = {
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"w30.d0", "w30.d1", "w31.d0", "w31.d1",
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};
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static const char * const mxuregnames[] = {
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"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
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"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
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};
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#define LOG_DISAS(...) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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@ -27231,6 +27240,17 @@ void mips_tcg_init(void)
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fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUMIPSState, active_fpu.fcr31),
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"fcr31");
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for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
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mxu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState,
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active_tc.mxu_gpr[i]),
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mxuregnames[i]);
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}
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mxu_CR = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.mxu_cr),
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mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
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}
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#include "translate_init.inc.c"
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