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target/mips: Remove vendor specific CPU definitions

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Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-10 22:46:43 +01:00
parent fc63010e9b
commit eaca85763b
2 changed files with 7 additions and 10 deletions
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12
target/mips/cpu-defs.c.inc
View File

@ -531,7 +531,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 32,
.insn_flags = CPU_VR54XX,
.insn_flags = CPU_MIPS4 | INSN_VR54XX,
.mmu_type = MMU_TYPE_R4000,
},
{
@ -781,7 +781,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2E,
.insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
.mmu_type = MMU_TYPE_R4000,
},
{
@ -801,7 +801,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2F,
.insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
.mmu_type = MMU_TYPE_R4000,
},
{
@ -830,7 +830,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 48,
.insn_flags = CPU_LOONGSON3A,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
@ -887,7 +888,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_LOONGSON3A,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{

5
target/mips/mips-defs.h
View File

@ -60,9 +60,6 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
#define CPU_MIPS64 (ISA_MIPS3)
@ -86,8 +83,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.