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target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags
We are close to running out of TB flags for AArch32; we could start using the cs_base word, but before we do that we can economise on our usage by sharing the same bits for the VFP VECSTRIDE field and the XScale XSCALE_CPAR field. This works because no XScale CPU ever had VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-18-peter.maydell@linaro.org
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@ -1034,6 +1034,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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set_feature(env, ARM_FEATURE_THUMB_DSP);
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}
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/*
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* We rely on no XScale CPU having VFP so we can use the same bits in the
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* TB flags field for VECSTRIDE and XSCALE_CPAR.
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*/
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assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
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arm_feature(env, ARM_FEATURE_XSCALE)));
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if (arm_feature(env, ARM_FEATURE_V7) &&
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!arm_feature(env, ARM_FEATURE_M) &&
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!arm_feature(env, ARM_FEATURE_PMSA)) {
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@ -3138,6 +3138,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
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FIELD(TBFLAG_A32, THUMB, 0, 1)
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FIELD(TBFLAG_A32, VECLEN, 1, 3)
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FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
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/*
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* We store the bottom two bits of the CPAR as TB flags and handle
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* checks on the other bits at runtime. This shares the same bits as
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* VECSTRIDE, which is OK as no XScale CPU has VFP.
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*/
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FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
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/*
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* Indicates whether cp register reads and writes by guest code should access
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* the secure or nonsecure bank of banked registers; note that this is not
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@ -3147,10 +3153,6 @@ FIELD(TBFLAG_A32, NS, 6, 1)
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FIELD(TBFLAG_A32, VFPEN, 7, 1)
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FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
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FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
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/* We store the bottom two bits of the CPAR as TB flags and handle
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* checks on the other bits at runtime
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*/
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FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2)
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/* For M profile only, Handler (ie not Thread) mode */
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FIELD(TBFLAG_A32, HANDLER, 21, 1)
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/* For M profile only, whether we should generate stack-limit checks */
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@ -13370,7 +13370,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
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flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
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}
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flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar);
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/* Note that XSCALE_CPAR shares bits with VECSTRIDE */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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flags = FIELD_DP32(flags, TBFLAG_A32,
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XSCALE_CPAR, env->cp15.c15_cpar);
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}
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}
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flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
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@ -13330,8 +13330,13 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
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dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
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dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
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dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
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dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
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dc->vec_stride = 0;
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} else {
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dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
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dc->c15_cpar = 0;
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}
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dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER);
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dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
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regime_is_secure(env, dc->mmu_idx);
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