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lm32: timer model
This patch adds support for the LatticeMico32 system timer. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Michael Walle
Edgar E. Iglesias
parent
f89286ae45
commit
ea7924dcc4
@ -250,6 +250,7 @@ obj-ppc-y += xilinx_ethlite.o
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# LM32 peripherals
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obj-lm32-y += lm32_pic.o
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obj-lm32-y += lm32_juart.o
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obj-lm32-y += lm32_timer.o
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obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
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obj-mips-y += mips_addr.o mips_timer.o mips_int.o
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222
hw/lm32_timer.c
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222
hw/lm32_timer.c
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@ -0,0 +1,222 @@
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/*
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* QEMU model of the LatticeMico32 timer block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.latticesemi.com/documents/mico32timer.pdf
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-timer.h"
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#include "qemu-error.h"
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#define DEFAULT_FREQUENCY (50*1000000)
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enum {
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R_SR = 0,
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R_CR,
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R_PERIOD,
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R_SNAPSHOT,
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R_MAX
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};
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enum {
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SR_TO = (1 << 0),
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SR_RUN = (1 << 1),
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};
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enum {
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CR_ITO = (1 << 0),
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CR_CONT = (1 << 1),
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CR_START = (1 << 2),
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CR_STOP = (1 << 3),
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};
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struct LM32TimerState {
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SysBusDevice busdev;
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QEMUBH *bh;
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ptimer_state *ptimer;
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qemu_irq irq;
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uint32_t freq_hz;
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uint32_t regs[R_MAX];
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};
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typedef struct LM32TimerState LM32TimerState;
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static void timer_update_irq(LM32TimerState *s)
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{
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int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
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trace_lm32_timer_irq_state(state);
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qemu_set_irq(s->irq, state);
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}
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static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
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{
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LM32TimerState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_SR:
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case R_CR:
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case R_PERIOD:
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r = s->regs[addr];
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break;
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case R_SNAPSHOT:
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r = (uint32_t)ptimer_get_count(s->ptimer);
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break;
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default:
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error_report("lm32_timer: read access to unkown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_lm32_timer_memory_read(addr << 2, r);
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return r;
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}
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static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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LM32TimerState *s = opaque;
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trace_lm32_timer_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_SR:
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s->regs[R_SR] &= ~SR_TO;
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break;
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case R_CR:
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s->regs[R_CR] = value;
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if (s->regs[R_CR] & CR_START) {
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ptimer_run(s->ptimer, 1);
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}
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if (s->regs[R_CR] & CR_STOP) {
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ptimer_stop(s->ptimer);
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}
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break;
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case R_PERIOD:
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s->regs[R_PERIOD] = value;
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ptimer_set_count(s->ptimer, value);
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break;
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case R_SNAPSHOT:
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error_report("lm32_timer: write access to read only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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error_report("lm32_timer: write access to unkown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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timer_update_irq(s);
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}
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static CPUReadMemoryFunc * const timer_read_fn[] = {
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NULL,
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NULL,
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&timer_read,
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};
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static CPUWriteMemoryFunc * const timer_write_fn[] = {
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NULL,
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NULL,
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&timer_write,
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};
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static void timer_hit(void *opaque)
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{
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LM32TimerState *s = opaque;
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trace_lm32_timer_hit();
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s->regs[R_SR] |= SR_TO;
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if (s->regs[R_CR] & CR_CONT) {
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ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
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ptimer_run(s->ptimer, 1);
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}
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timer_update_irq(s);
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}
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static void timer_reset(DeviceState *d)
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{
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LM32TimerState *s = container_of(d, LM32TimerState, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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ptimer_stop(s->ptimer);
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}
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static int lm32_timer_init(SysBusDevice *dev)
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{
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LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
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int timer_regs;
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sysbus_init_irq(dev, &s->irq);
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s->bh = qemu_bh_new(timer_hit, s);
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s->ptimer = ptimer_init(s->bh);
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ptimer_set_freq(s->ptimer, s->freq_hz);
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timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, R_MAX * 4, timer_regs);
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return 0;
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}
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static const VMStateDescription vmstate_lm32_timer = {
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.name = "lm32-timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(ptimer, LM32TimerState),
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VMSTATE_UINT32(freq_hz, LM32TimerState),
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VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static SysBusDeviceInfo lm32_timer_info = {
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.init = lm32_timer_init,
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.qdev.name = "lm32-timer",
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.qdev.size = sizeof(LM32TimerState),
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.qdev.vmsd = &vmstate_lm32_timer,
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.qdev.reset = timer_reset,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32(
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"frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY
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),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void lm32_timer_register(void)
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{
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sysbus_register_withprop(&lm32_timer_info);
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}
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device_init(lm32_timer_register)
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@ -269,3 +269,9 @@ disable lm32_juart_get_jtx(uint32_t value) "jtx 0x%08x"
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disable lm32_juart_set_jtx(uint32_t value) "jtx 0x%08x"
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disable lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x"
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disable lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x"
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# hw/lm32_timer.c
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disable lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_timer_hit(void) "timer hit"
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disable lm32_timer_irq_state(int level) "irq state %d"
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