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Try to avoid glibc global register mangling, again

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-07-26 17:19:35 +00:00
parent 2991990b18
commit e97b640d47
4 changed files with 45 additions and 26 deletions
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6
Makefile.target
View File

@ -121,10 +121,12 @@ ifeq ($(ARCH),sparc)
endif endif
ifeq ($(ARCH),sparc64) ifeq ($(ARCH),sparc64)
CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7
OP_CFLAGS+=-mcpu=ultrasparc -m64 -fno-delayed-branch -ffixed-i0 OP_CFLAGS+=-mcpu=ultrasparc -m64 -fno-delayed-branch -ffixed-i0
ifneq ($(CONFIG_SOLARIS),yes) ifneq ($(CONFIG_SOLARIS),yes)
OP_CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7 CFLAGS+=-ffixed-g5 -ffixed-g6 -ffixed-g7
OP_CFLAGS+=-ffixed-g5 -ffixed-g6 -ffixed-g7
else
CFLAGS+=-ffixed-g1 -ffixed-g4 -ffixed-g5 -ffixed-g7
endif endif
endif endif

7
dyngen-exec.h
View File

@ -146,10 +146,9 @@ extern int printf(const char *, ...);
#define AREG4 "g6" #define AREG4 "g6"
#else #else
#ifdef __sparc_v9__ #ifdef __sparc_v9__
#define AREG0 "g1" #define AREG0 "g5"
#define AREG1 "g4" #define AREG1 "g6"
#define AREG2 "g5" #define AREG2 "g7"
#define AREG3 "g7"
#else #else
#define AREG0 "g6" #define AREG0 "g6"
#define AREG1 "g1" #define AREG1 "g1"

38
tcg/sparc/tcg-target.c
View File

@ -839,16 +839,34 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
break; break;
case INDEX_op_call: case INDEX_op_call:
if (const_args[0]) { {
tcg_out32(s, CALL | ((((tcg_target_ulong)args[0] unsigned int st_op, ld_op;
- (tcg_target_ulong)s->code_ptr) >> 2)
& 0x3fffffff)); #ifdef __arch64__
tcg_out_nop(s); st_op = STX;
} else { ld_op = LDX;
tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0])); #else
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | st_op = STW;
INSN_RS2(TCG_REG_G0)); ld_op = LDUW;
tcg_out_nop(s); #endif
if (const_args[0])
tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
- (tcg_target_ulong)s->code_ptr) >> 2)
& 0x3fffffff));
else {
tcg_out_ld_ptr(s, TCG_REG_I5,
(tcg_target_long)(s->tb_next + args[0]));
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
INSN_RS2(TCG_REG_G0));
}
/* Store AREG0 in stack to avoid ugly glibc bugs that mangle
global registers */
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
st_op); // delay slot
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
TCG_TARGET_CALL_STACK_OFFSET - sizeof(long),
ld_op);
} }
break; break;
case INDEX_op_jmp: case INDEX_op_jmp:

20
tcg/sparc/tcg-target.h
View File

@ -72,14 +72,15 @@ enum {
#define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_S13 0x200
/* used for function call generation */ /* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_O6 #define TCG_REG_CALL_STACK TCG_REG_I6
#ifdef __arch64__ #ifdef __arch64__
#define TCG_TARGET_STACK_MINFRAME 176 // Reserve space for AREG0
#define TCG_TARGET_CALL_STACK_OFFSET (2047 + 176) #define TCG_TARGET_STACK_MINFRAME (176 + 2 * sizeof(long))
#define TCG_TARGET_CALL_STACK_OFFSET (2047 + TCG_TARGET_STACK_MINFRAME)
#define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_STACK_ALIGN 16
#else #else
#define TCG_TARGET_STACK_MINFRAME 92 #define TCG_TARGET_STACK_MINFRAME (92 + 2 * sizeof(long))
#define TCG_TARGET_CALL_STACK_OFFSET 92 #define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
#define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_STACK_ALIGN 8
#endif #endif
@ -90,7 +91,7 @@ enum {
//#define TCG_TARGET_HAS_neg_i64 //#define TCG_TARGET_HAS_neg_i64
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h and Makefile.target */
#ifdef HOST_SOLARIS #ifdef HOST_SOLARIS
#define TCG_AREG0 TCG_REG_G2 #define TCG_AREG0 TCG_REG_G2
#define TCG_AREG1 TCG_REG_G3 #define TCG_AREG1 TCG_REG_G3
@ -98,10 +99,9 @@ enum {
#define TCG_AREG3 TCG_REG_G5 #define TCG_AREG3 TCG_REG_G5
#define TCG_AREG4 TCG_REG_G6 #define TCG_AREG4 TCG_REG_G6
#elif defined(__sparc_v9__) #elif defined(__sparc_v9__)
#define TCG_AREG0 TCG_REG_G1 #define TCG_AREG0 TCG_REG_G5
#define TCG_AREG1 TCG_REG_G4 #define TCG_AREG1 TCG_REG_G6
#define TCG_AREG2 TCG_REG_G5 #define TCG_AREG2 TCG_REG_G7
#define TCG_AREG3 TCG_REG_G7
#else #else
#define TCG_AREG0 TCG_REG_G6 #define TCG_AREG0 TCG_REG_G6
#define TCG_AREG1 TCG_REG_G1 #define TCG_AREG1 TCG_REG_G1