mirrors/qemu
0
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2024-11-27 05:43:47 +08:00
Code Issues Packages Projects Releases Wiki Activity

tcg/ppc64: Fix zero extension code generation bug for ppc64 host

Browse Source 
The ppc64 code generation backend uses an rldicr (Rotate Left Double
Immediate and Clear Right) instruction to implement zero extension of
a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64).  However
this is wrong - this instruction clears specified low bits of the
value, instead of high bits as we require for a zero extension.  It
should instead use an rldicl (Rotate Left Double Immediate and Clear
Left) instruction.

Presumably amongst other things, this causes the SLOF firmware image
used with -M pseries to not boot on a ppc64 host.

It appears this bug was exposed by commit
0bf1dbdcc9 (tcg/ppc64: fix 16/32 mixup)
which enabled the use of the op_ext32u_i64 operation on the ppc64
backend.

Signed-off-by: Thomas Huth <thuth@de.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
Thomas Huth 2011-09-09 15:58:37 +10:00 committed by malc
parent 07ff2c4475
commit e89720b116
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tcg/ppc64/tcg-target.c
View File

@ -1560,7 +1560,7 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_ext32u_i64:
tcg_out_rld (s, RLDICR, args[0], args[1], 0, 32);
tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32);
break;
case INDEX_op_setcond_i32: