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target-sparc: fix FMOVr instruction

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Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Aurelien Jarno 2012-10-17 01:28:35 +02:00 committed by Blue Swirl
parent a5089c0501
commit e7c8afb905
1 changed files with 1 additions and 1 deletions
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2
target-sparc/translate.c
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@ -3176,7 +3176,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#define FMOVR(sz) \
do { \
DisasCompare cmp; \
cond = GET_FIELD_SP(insn, 14, 17); \
cond = GET_FIELD_SP(insn, 10, 12); \
cpu_src1 = get_src1(dc, insn); \
gen_compare_reg(&cmp, cond, cpu_src1); \
gen_fmov##sz(dc, &cmp, rd, rs2); \