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Merge remote-tracking branch 'afaerber-or/qom-cpu-3a' into staging

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* afaerber-or/qom-cpu-3a: (27 commits)
  target-s390x: Pass S390CPU to s390_cpu_restart()
  s390-virtio: Let s390_cpu_addr2state() return S390CPU
  s390-virtio: Use cpu_s390x_init() to obtain S390CPU
  target-s390x: Let cpu_s390x_init() return S390CPU
  xen_machine_pv: Use cpu_x86_init() to obtain X86CPU
  arm_pic: Pass ARMCPU to arm_pic_init_cpu()
  arm_boot: Pass ARMCPU to arm_load_kernel()
  xilinx_zynq: Use cpu_arm_init() to obtain ARMCPU
  pxa2xx_gpio: Store ARMCPU in PXA2xxGPIOInfo
  pxa2xx_pic: Store ARMCPU in PXA2xxPICState
  pxa2xx: Pass ARMCPU to pxa2xx_pic_init()
  exynos4210: Use cpu_arm_init() to store ARMCPU
  vexpress: Use cpu_arm_init() to obtain ARMCPU
  realview: Use cpu_arm_init() to obtain ARMCPU
  arm_boot: Pass ARMCPU to arm_boot_info::secondary_cpu_reset_hook()
  arm_boot: Pass ARMCPU to arm_boot_info::write_secondary_boot()
  versatilepb: Use cpu_arm_init() to obtain ARMCPU
  musicpal: Use cpu_arm_init() to obtain ARMCPU
  integratorcp: Use cpu_arm_init() to obtain ARMCPU
  strongarm: Use cpu_arm_init() to store ARMCPU in StrongARMState
  ...
This commit is contained in:
Anthony Liguori 2012-06-11 12:15:51 -05:00
commit e4d40816f1
37 changed files with 223 additions and 197 deletions
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8
hw/arm-misc.h
View File

@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUARMState *env);
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
@ -50,16 +50,16 @@ struct arm_boot_info {
* perform any necessary CPU reset handling and set the PC for thei
* secondary CPUs to point at this boot blob.
*/
void (*write_secondary_boot)(CPUARMState *env,
void (*write_secondary_boot)(ARMCPU *cpu,
const struct arm_boot_info *info);
void (*secondary_cpu_reset_hook)(CPUARMState *env,
void (*secondary_cpu_reset_hook)(ARMCPU *cpu,
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
};
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */

14
hw/arm_boot.c
View File

@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
0 /* bootreg: Boot register address is held here */
};
static void default_write_secondary(CPUARMState *env,
static void default_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
int n;
@ -72,9 +72,11 @@ static void default_write_secondary(CPUARMState *env,
info->smp_loader_start);
}
static void default_reset_secondary(CPUARMState *env,
static void default_reset_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
CPUARMState *env = &cpu->env;
stl_phys_notdirty(info->smp_bootreg_addr, 0);
env->regs[15] = info->smp_loader_start;
}
@ -295,15 +297,15 @@ static void do_cpu_reset(void *opaque)
}
}
} else {
info->secondary_cpu_reset_hook(env, info);
info->secondary_cpu_reset_hook(cpu, info);
}
}
}
}
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
{
ARMCPU *cpu;
CPUARMState *env = &cpu->env;
int kernel_size;
int initrd_size;
int n;
@ -402,7 +404,7 @@ void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
info->loader_start);
if (info->nb_cpus > 1) {
info->write_secondary_boot(env, info);
info->write_secondary_boot(cpu, info);
}
}
info->is_linux = is_linux;

8
hw/arm_pic.c
View File

@ -13,7 +13,9 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUARMState *env = (CPUARMState *)opaque;
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@ -32,7 +34,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
qemu_irq *arm_pic_init_cpu(CPUARMState *env)
qemu_irq *arm_pic_init_cpu(ARMCPU *cpu)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
return qemu_allocate_irqs(arm_pic_cpu_handler, cpu, 2);
}

2
hw/armv7m.c
View File

@ -215,7 +215,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
nvic = qdev_create(NULL, "armv7m_nvic");
env->nvic = nvic;
qdev_init_nofail(nvic);
cpu_pic = arm_pic_init_cpu(env);
cpu_pic = arm_pic_init_cpu(cpu);
sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
for (i = 0; i < 64; i++) {
pic[i] = qdev_get_gpio_in(nvic, i);

2
hw/collie.c
View File

@ -54,7 +54,7 @@ static void collie_init(ram_addr_t ram_size,
collie_binfo.kernel_cmdline = kernel_cmdline;
collie_binfo.initrd_filename = initrd_filename;
collie_binfo.board_id = 0x208;
arm_load_kernel(s->env, &collie_binfo);
arm_load_kernel(s->cpu, &collie_binfo);
}
static QEMUMachine collie_machine = {

9
hw/exynos4210.c
View File

@ -65,7 +65,7 @@
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
void exynos4210_write_secondary(CPUARMState *env,
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info)
{
int n;
@ -107,13 +107,14 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
SysBusDevice *busdev;
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
s->env[n] = cpu_init("cortex-a9");
if (!s->env[n]) {
s->cpu[n] = cpu_arm_init("cortex-a9");
if (!s->cpu[n]) {
fprintf(stderr, "Unable to find CPU %d definition\n", n);
exit(1);
}
/* Create PIC controller for each processor instance */
irqp = arm_pic_init_cpu(s->env[n]);
irqp = arm_pic_init_cpu(s->cpu[n]);
/*
* Get GICs gpio_in cpu_irq to connect a combiner to them later.

4
hw/exynos4210.h
View File

@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
} Exynos4210Irq;
typedef struct Exynos4210State {
CPUARMState * env[EXYNOS4210_NCPUS];
ARMCPU *cpu[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;
@ -97,7 +97,7 @@ typedef struct Exynos4210State {
MemoryRegion bootreg_mem;
} Exynos4210State;
void exynos4210_write_secondary(CPUARMState *env,
void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info);
Exynos4210State *exynos4210_init(MemoryRegion *system_mem,

4
hw/exynos4_boards.c
View File

@ -138,7 +138,7 @@ static void nuri_init(ram_addr_t ram_size,
exynos4_boards_init_common(kernel_filename, kernel_cmdline,
initrd_filename, EXYNOS4_BOARD_NURI);
arm_load_kernel(first_cpu, &exynos4_board_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &exynos4_board_binfo);
}
static void smdkc210_init(ram_addr_t ram_size,
@ -151,7 +151,7 @@ static void smdkc210_init(ram_addr_t ram_size,
lan9215_init(SMDK_LAN9118_BASE_ADDR,
qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)]));
arm_load_kernel(first_cpu, &exynos4_board_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &exynos4_board_binfo);
}
static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS] = {

13
hw/highbank.c
View File

@ -36,7 +36,7 @@
/* Board init. */
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
int n;
uint32_t smpboot[] = {
@ -60,8 +60,10 @@ static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *inf
rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}
static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
CPUARMState *env = &cpu->env;
switch (info->nb_cpus) {
case 4:
stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
@ -190,7 +192,6 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;
@ -213,10 +214,10 @@ static void highbank_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* This will become a QOM property eventually */
cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
@ -316,7 +317,7 @@ static void highbank_init(ram_addr_t ram_size,
highbank_binfo.loader_start = 0;
highbank_binfo.write_secondary_boot = hb_write_secondary;
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
arm_load_kernel(first_cpu, &highbank_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo);
}
static QEMUMachine highbank_machine = {

14
hw/integratorcp.c
View File

@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
@ -452,13 +452,15 @@ static void integratorcp_init(ram_addr_t ram_size,
DeviceState *dev;
int i;
if (!cpu_model)
if (!cpu_model) {
cpu_model = "arm926";
env = cpu_init(cpu_model);
if (!env) {
}
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
memory_region_init_ram(ram, "integrator.ram", ram_size);
vmstate_register_ram_global(ram);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
@ -474,7 +476,7 @@ static void integratorcp_init(ram_addr_t ram_size,
qdev_init_nofail(dev);
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(env);
cpu_pic = arm_pic_init_cpu(cpu);
dev = sysbus_create_varargs("integrator_pic", 0x14000000,
cpu_pic[ARM_PIC_CPU_IRQ],
cpu_pic[ARM_PIC_CPU_FIQ], NULL);
@ -500,7 +502,7 @@ static void integratorcp_init(ram_addr_t ram_size,
integrator_binfo.kernel_filename = kernel_filename;
integrator_binfo.kernel_cmdline = kernel_cmdline;
integrator_binfo.initrd_filename = initrd_filename;
arm_load_kernel(env, &integrator_binfo);
arm_load_kernel(cpu, &integrator_binfo);
}
static QEMUMachine integratorcp_machine = {

16
hw/mainstone.c
View File

@ -102,7 +102,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
{
uint32_t sector_len = 256 * 1024;
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
PXA2xxState *mpu;
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
@ -113,7 +113,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
cpu_model = "pxa270-c5";
/* Setup CPU & memory */
cpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
memory_region_init_ram(rom, "mainstone.rom", MAINSTONE_ROM);
vmstate_register_ram_global(rom);
memory_region_set_readonly(rom, true);
@ -145,19 +145,19 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
}
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
qdev_get_gpio_in(cpu->gpio, 0));
qdev_get_gpio_in(mpu->gpio, 0));
/* setup keypad */
printf("map addr %p\n", &map);
pxa27x_register_keypad(cpu->kp, map, 0xe0);
pxa27x_register_keypad(mpu->kp, map, 0xe0);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
qdev_get_gpio_in(mst_irq, S0_IRQ),
qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
qdev_get_gpio_in(mst_irq, S1_IRQ),
qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
@ -168,7 +168,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
mainstone_binfo.kernel_cmdline = kernel_cmdline;
mainstone_binfo.initrd_filename = initrd_filename;
mainstone_binfo.board_id = arm_id;
arm_load_kernel(&cpu->cpu->env, &mainstone_binfo);
arm_load_kernel(mpu->cpu, &mainstone_binfo);
}
static void mainstone_init(ram_addr_t ram_size,

10
hw/musicpal.c
View File

@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env;
ARMCPU *cpu;
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;
@ -1533,12 +1533,12 @@ static void musicpal_init(ram_addr_t ram_size,
if (!cpu_model) {
cpu_model = "arm926";
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
cpu_pic = arm_pic_init_cpu(env);
cpu_pic = arm_pic_init_cpu(cpu);
/* For now we use a fixed - the original - RAM size */
memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
@ -1651,7 +1651,7 @@ static void musicpal_init(ram_addr_t ram_size,
musicpal_binfo.kernel_filename = kernel_filename;
musicpal_binfo.kernel_cmdline = kernel_cmdline;
musicpal_binfo.initrd_filename = initrd_filename;
arm_load_kernel(env, &musicpal_binfo);
arm_load_kernel(cpu, &musicpal_binfo);
}
static QEMUMachine musicpal_machine = {

72
hw/nseries.c
View File

@ -37,7 +37,7 @@
/* Nokia N8x0 support */
struct n800_s {
struct omap_mpu_state_s *cpu;
struct omap_mpu_state_s *mpu;
struct rfbi_chip_s blizzard;
struct {
@ -135,10 +135,10 @@ static void n800_mmc_cs_cb(void *opaque, int line, int level)
static void n8x0_gpio_setup(struct n800_s *s)
{
qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
}
#define MAEMO_CAL_HEADER(...) \
@ -179,8 +179,8 @@ static void n8x0_nand_setup(struct n800_s *s)
}
qdev_init_nofail(s->nand);
sysbus_connect_irq(sysbus_from_qdev(s->nand), 0,
qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS,
qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0));
otp_region = onenand_raw_otp(s->nand);
@ -192,13 +192,13 @@ static void n8x0_nand_setup(struct n800_s *s)
static void n8x0_i2c_setup(struct n800_s *s)
{
DeviceState *dev;
qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
i2c_bus *i2c = omap_i2c_bus(s->cpu->i2c[0]);
qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
/* Attach a menelaus PM chip */
dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
qdev_connect_gpio_out(dev, 3,
qdev_get_gpio_in(s->cpu->ih[0],
qdev_get_gpio_in(s->mpu->ih[0],
OMAP_INT_24XX_SYS_NIRQ));
qemu_system_powerdown = qdev_get_gpio_in(dev, 3);
@ -263,8 +263,8 @@ static void n800_tsc_kbd_setup(struct n800_s *s)
/* XXX: are the three pins inverted inside the chip between the
* tsc and the cpu (N4111)? */
qemu_irq penirq = NULL; /* NC */
qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
s->ts.chip = tsc2301_init(penirq, kbirq, dav);
s->ts.opaque = s->ts.chip->opaque;
@ -283,7 +283,7 @@ static void n800_tsc_kbd_setup(struct n800_s *s)
static void n810_tsc_setup(struct n800_s *s)
{
qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
s->ts.opaque = tsc2005_init(pintdav);
s->ts.txrx = tsc2005_txrx;
@ -375,7 +375,7 @@ static int n810_keys[0x80] = {
static void n810_kbd_setup(struct n800_s *s)
{
qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
int i;
for (i = 0; i < 0x80; i ++)
@ -388,7 +388,7 @@ static void n810_kbd_setup(struct n800_s *s)
/* Attach the LM8322 keyboard to the I2C bus,
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
s->kbd = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[0]),
s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
"lm8323", N810_LM8323_ADDR);
qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
}
@ -679,8 +679,8 @@ static void n8x0_spi_setup(struct n800_s *s)
void *tsc = s->ts.opaque;
void *mipid = mipid_init();
omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
}
/* This task is normally performed by the bootloader. If we're loading
@ -735,20 +735,20 @@ static void n8x0_dss_setup(struct n800_s *s)
s->blizzard.write = s1d13745_write;
s->blizzard.read = s1d13745_read;
omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
}
static void n8x0_cbus_setup(struct n800_s *s)
{
qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
CBus *cbus = cbus_init(dat_out);
qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
@ -757,14 +757,14 @@ static void n8x0_cbus_setup(struct n800_s *s)
static void n8x0_uart_setup(struct n800_s *s)
{
CharDriverState *radio = uart_hci_init(
qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
csrhci_pins_get(radio)[csrhci_pin_reset]);
qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
csrhci_pins_get(radio)[csrhci_pin_wakeup]);
omap_uart_attach(s->cpu->uart[BT_UART], radio);
omap_uart_attach(s->mpu->uart[BT_UART], radio);
}
static void n8x0_usb_setup(struct n800_s *s)
@ -774,13 +774,13 @@ static void n8x0_usb_setup(struct n800_s *s)
dev = sysbus_from_qdev(s->usb);
qdev_init_nofail(s->usb);
sysbus_connect_irq(dev, 0,
qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO));
qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
/* Using the NOR interface */
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
sysbus_mmio_get_region(dev, 0));
omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
sysbus_mmio_get_region(dev, 1));
qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO,
qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
}
@ -1023,11 +1023,11 @@ static void n8x0_boot_init(void *opaque)
n800_dss_init(&s->blizzard);
/* CPU setup */
s->cpu->cpu->env.GE = 0x5;
s->mpu->cpu->env.GE = 0x5;
/* If the machine has a slided keyboard, open it */
if (s->kbd)
qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
}
#define OMAP_TAG_NOKIA_BT 0x4e01
@ -1281,7 +1281,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
int sdram_size = binfo->ram_size;
DisplayState *ds;
s->cpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model);
s->mpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model);
/* Setup peripherals
*
@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
binfo->kernel_filename = kernel_filename;
binfo->kernel_cmdline = kernel_cmdline;
binfo->initrd_filename = initrd_filename;
arm_load_kernel(&s->cpu->cpu->env, binfo);
arm_load_kernel(s->mpu->cpu, binfo);
qemu_register_reset(n8x0_boot_init, s);
}
@ -1338,7 +1338,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
int rom_size;
uint8_t nolo_tags[0x10000];
/* No, wait, better start at the ROM. */
s->cpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
/* This is intended for loading the `secondary.bin' program from
* Nokia images (the NOLO bootloader). The entry point seems

2
hw/omap1.c
View File

@ -3854,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(&s->cpu->env);
cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));

2
hw/omap2.c
View File

@ -2277,7 +2277,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
cpu_irq = arm_pic_init_cpu(&s->cpu->env);
cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));

6
hw/omap_sx1.c
View File

@ -103,7 +103,7 @@ static void sx1_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
const int version)
{
struct omap_mpu_state_s *cpu;
struct omap_mpu_state_s *mpu;
MemoryRegion *address_space = get_system_memory();
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
@ -121,7 +121,7 @@ static void sx1_init(ram_addr_t ram_size,
flash_size = flash2_size;
}
cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size);
@ -202,7 +202,7 @@ static void sx1_init(ram_addr_t ram_size,
sx1_binfo.kernel_filename = kernel_filename;
sx1_binfo.kernel_cmdline = kernel_cmdline;
sx1_binfo.initrd_filename = initrd_filename;
arm_load_kernel(&cpu->cpu->env, &sx1_binfo);
arm_load_kernel(mpu->cpu, &sx1_binfo);
}
/* TODO: fix next line */

12
hw/palm.c
View File

@ -196,7 +196,7 @@ static void palmte_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *cpu;
struct omap_mpu_state_s *mpu;
int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size;
static uint32_t cs0val = 0xffffffff;
@ -208,7 +208,7 @@ static void palmte_init(ram_addr_t ram_size,
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, "palmte.flash", flash_size);
@ -230,11 +230,11 @@ static void palmte_init(ram_addr_t ram_size,
OMAP_CS3_SIZE);
memory_region_add_subregion(address_space_mem, OMAP_CS3_BASE, &cs[3]);
palmte_microwire_setup(cpu);
palmte_microwire_setup(mpu);
qemu_add_kbd_event_handler(palmte_button_event, cpu);
qemu_add_kbd_event_handler(palmte_button_event, mpu);
palmte_gpio_setup(cpu);
palmte_gpio_setup(mpu);
/* Setup initial (reset) machine state */
if (nb_option_roms) {
@ -265,7 +265,7 @@ static void palmte_init(ram_addr_t ram_size,
palmte_binfo.kernel_filename = kernel_filename;
palmte_binfo.kernel_cmdline = kernel_cmdline;
palmte_binfo.initrd_filename = initrd_filename;
arm_load_kernel(&cpu->cpu->env, &palmte_binfo);
arm_load_kernel(mpu->cpu, &palmte_binfo);
}
/* FIXME: We shouldn't really be doing this here. The LCD controller

2
hw/pxa.h
View File

@ -65,7 +65,7 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,

4
hw/pxa2xx.c
View File

@ -2081,7 +2081,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
&s->internal);
s->pic = pxa2xx_pic_init(0x40d00000, &s->cpu->env);
s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
s->dma = pxa27x_dma_init(0x40000000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
@ -2213,7 +2213,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
&s->internal);
s->pic = pxa2xx_pic_init(0x40d00000, &s->cpu->env);
s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
s->dma = pxa255_dma_init(0x40000000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));

9
hw/pxa2xx_gpio.c
View File

@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
CPUARMState *cpu_env;
ARMCPU *cpu;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@ -118,8 +118,9 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level)
pxa2xx_gpio_irq_update(s);
/* Wake-up GPIOs */
if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
if (s->cpu->env.halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
}
}
static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
@ -275,7 +276,7 @@ static int pxa2xx_gpio_initfn(SysBusDevice *dev)
s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
s->cpu_env = qemu_get_cpu(s->ncpu);
s->cpu = arm_env_get_cpu(qemu_get_cpu(s->ncpu));
qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);

32
hw/pxa2xx_pic.c
View File

@ -34,7 +34,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
CPUARMState *cpu_env;
ARMCPU *cpu;
uint32_t int_enabled[2];
uint32_t int_pending[2];
uint32_t is_fiq[2];
@ -47,25 +47,28 @@ static void pxa2xx_pic_update(void *opaque)
uint32_t mask[2];
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
if (s->cpu_env->halted) {
if (s->cpu->env.halted) {
mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
if (mask[0] || mask[1])
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
if (mask[0] || mask[1]) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
}
}
mask[0] = s->int_pending[0] & s->int_enabled[0];
mask[1] = s->int_pending[1] & s->int_enabled[1];
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
else
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
} else {
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
}
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1]))
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
else
cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
}
}
/* Note: Here level means state of the signal on a pin, not
@ -245,12 +248,13 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu)
{
CPUARMState *env = &cpu->env;
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
s->cpu_env = env;
s->cpu = cpu;
s->int_pending[0] = 0;
s->int_pending[1] = 0;

12
hw/realview.c
View File

@ -50,7 +50,8 @@ static void realview_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
enum realview_board_type board_type)
{
CPUARMState *env = NULL;
ARMCPU *cpu = NULL;
CPUARMState *env;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
@ -88,14 +89,15 @@ static void realview_init(ram_addr_t ram_size,
break;
}
for (n = 0; n < smp_cpus; n++) {
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_V7)) {
if (is_mpcore) {
proc_id = 0x0c000000;
@ -325,7 +327,7 @@ static void realview_init(ram_addr_t ram_size,
realview_binfo.nb_cpus = smp_cpus;
realview_binfo.board_id = realview_board_id[board_type];
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
arm_load_kernel(first_cpu, &realview_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &realview_binfo);
}
static void realview_eb_init(ram_addr_t ram_size,

6
hw/s390-virtio-bus.c
View File

@ -140,7 +140,8 @@ static int s390_virtio_device_init(VirtIOS390Device *dev, VirtIODevice *vdev)
s390_virtio_device_sync(dev);
s390_virtio_reset_idx(dev);
if (dev->qdev.hotplugged) {
CPUS390XState *env = s390_cpu_addr2state(0);
S390CPU *cpu = s390_cpu_addr2state(0);
CPUS390XState *env = &cpu->env;
s390_virtio_irq(env, VIRTIO_PARAM_DEV_ADD, dev->dev_offs);
}
@ -354,7 +355,8 @@ static void virtio_s390_notify(void *opaque, uint16_t vector)
{
VirtIOS390Device *dev = (VirtIOS390Device*)opaque;
uint64_t token = s390_virtio_device_vq_token(dev, vector);
CPUS390XState *env = s390_cpu_addr2state(0);
S390CPU *cpu = s390_cpu_addr2state(0);
CPUS390XState *env = &cpu->env;
s390_virtio_irq(env, 0, token);
}

12
hw/s390-virtio.c
View File

@ -61,9 +61,9 @@
#define MAX_BLK_DEVS 10
static VirtIOS390Bus *s390_bus;
static CPUS390XState **ipi_states;
static S390CPU **ipi_states;
CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr)
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr)
{
if (cpu_addr >= smp_cpus) {
return NULL;
@ -206,16 +206,18 @@ static void s390_init(ram_addr_t my_ram_size,
cpu_model = "host";
}
ipi_states = g_malloc(sizeof(CPUS390XState *) * smp_cpus);
ipi_states = g_malloc(sizeof(S390CPU *) * smp_cpus);
for (i = 0; i < smp_cpus; i++) {
S390CPU *cpu;
CPUS390XState *tmp_env;
tmp_env = cpu_init(cpu_model);
cpu = cpu_s390x_init(cpu_model);
tmp_env = &cpu->env;
if (!env) {
env = tmp_env;
}
ipi_states[i] = tmp_env;
ipi_states[i] = cpu;
tmp_env->halted = 1;
tmp_env->exception_index = EXCP_HLT;
tmp_env->storage_keys = storage_keys;

24
hw/spitz.c
View File

@ -884,7 +884,7 @@ static void spitz_common_init(ram_addr_t ram_size,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum spitz_model_e model, int arm_id)
{
PXA2xxState *cpu;
PXA2xxState *mpu;
DeviceState *scp0, *scp1 = NULL;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
@ -893,9 +893,9 @@ static void spitz_common_init(ram_addr_t ram_size,
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
/* Setup CPU & memory */
cpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
memory_region_init_ram(rom, "spitz.rom", SPITZ_ROM);
vmstate_register_ram_global(rom);
@ -903,36 +903,36 @@ static void spitz_common_init(ram_addr_t ram_size,
memory_region_add_subregion(address_space_mem, 0, rom);
/* Setup peripherals */
spitz_keyboard_register(cpu);
spitz_keyboard_register(mpu);
spitz_ssp_attach(cpu);
spitz_ssp_attach(mpu);
scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
if (model != akita) {
scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
}
spitz_scoop_gpio_setup(cpu, scp0, scp1);
spitz_scoop_gpio_setup(mpu, scp0, scp1);
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
spitz_i2c_setup(cpu);
spitz_i2c_setup(mpu);
if (model == akita)
spitz_akita_i2c_setup(cpu);
spitz_akita_i2c_setup(mpu);
if (model == terrier)
/* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
spitz_microdrive_attach(cpu, 1);
spitz_microdrive_attach(mpu, 1);
else if (model != akita)
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
spitz_microdrive_attach(cpu, 0);
spitz_microdrive_attach(mpu, 0);
spitz_binfo.kernel_filename = kernel_filename;
spitz_binfo.kernel_cmdline = kernel_cmdline;
spitz_binfo.initrd_filename = initrd_filename;
spitz_binfo.board_id = arm_id;
arm_load_kernel(&cpu->cpu->env, &spitz_binfo);
arm_load_kernel(mpu->cpu, &spitz_binfo);
sl_bootparam_write(SL_PXA_PARAM_BASE);
}

6
hw/strongarm.c
View File

@ -1563,9 +1563,9 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
exit(1);
}
s->env = cpu_init(rev);
s->cpu = cpu_arm_init(rev);
if (!s->env) {
if (!s->cpu) {
error_report("Unable to find CPU definition");
exit(1);
}
@ -1574,7 +1574,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem,
vmstate_register_ram_global(&s->sdram);
memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
pic = arm_pic_init_cpu(s->env);
pic = arm_pic_init_cpu(s->cpu);
s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);

2
hw/strongarm.h
View File

@ -53,7 +53,7 @@ enum {
};
typedef struct {
CPUARMState *env;
ARMCPU *cpu;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;

14
hw/tosa.c
View File

@ -212,14 +212,14 @@ static void tosa_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
PXA2xxState *cpu;
PXA2xxState *mpu;
TC6393xbState *tmio;
DeviceState *scp0, *scp1;
if (!cpu_model)
cpu_model = "pxa255";
cpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
memory_region_init_ram(rom, "tosa.rom", TOSA_ROM);
vmstate_register_ram_global(rom);
@ -227,22 +227,22 @@ static void tosa_init(ram_addr_t ram_size,
memory_region_add_subregion(address_space_mem, 0, rom);
tmio = tc6393xb_init(address_space_mem, 0x10000000,
qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_TC6393XB_INT));
qdev_get_gpio_in(mpu->gpio, TOSA_GPIO_TC6393XB_INT));
scp0 = sysbus_create_simple("scoop", 0x08800000, NULL);
scp1 = sysbus_create_simple("scoop", 0x14800040, NULL);
tosa_gpio_setup(cpu, scp0, scp1, tmio);
tosa_gpio_setup(mpu, scp0, scp1, tmio);
tosa_microdrive_attach(cpu);
tosa_microdrive_attach(mpu);
tosa_tg_init(cpu);
tosa_tg_init(mpu);
tosa_binfo.kernel_filename = kernel_filename;
tosa_binfo.kernel_cmdline = kernel_cmdline;
tosa_binfo.initrd_filename = initrd_filename;
tosa_binfo.board_id = 0x208;
arm_load_kernel(&cpu->cpu->env, &tosa_binfo);
arm_load_kernel(mpu->cpu, &tosa_binfo);
sl_bootparam_write(SL_PXA_PARAM_BASE);
}

13
hw/versatilepb.c
View File

@ -173,7 +173,7 @@ static void versatile_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
int board_id)
{
CPUARMState *env;
ARMCPU *cpu;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_pic;
@ -189,10 +189,11 @@ static void versatile_init(ram_addr_t ram_size,
int done_smc = 0;
DriveInfo *dinfo;
if (!cpu_model)
if (!cpu_model) {
cpu_model = "arm926";
env = cpu_init(cpu_model);
if (!env) {
}
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
@ -208,7 +209,7 @@ static void versatile_init(ram_addr_t ram_size,
qdev_init_nofail(sysctl);
sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
cpu_pic = arm_pic_init_cpu(env);
cpu_pic = arm_pic_init_cpu(cpu);
dev = sysbus_create_varargs("pl190", 0x10140000,
cpu_pic[0], cpu_pic[1], NULL);
for (n = 0; n < 32; n++) {
@ -338,7 +339,7 @@ static void versatile_init(ram_addr_t ram_size,
versatile_binfo.kernel_cmdline = kernel_cmdline;
versatile_binfo.initrd_filename = initrd_filename;
versatile_binfo.board_id = board_id;
arm_load_kernel(env, &versatile_binfo);
arm_load_kernel(cpu, &versatile_binfo);
}
static void vpb_init(ram_addr_t ram_size,

18
hw/vexpress.c
View File

@ -159,7 +159,6 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
{
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
@ -177,12 +176,12 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
*proc_id = 0x0c000191;
for (n = 0; n < smp_cpus; n++) {
env = cpu_init(cpu_model);
if (!env) {
ARMCPU *cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
@ -259,7 +258,6 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
qemu_irq *pic, uint32_t *proc_id)
{
int n;
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
@ -274,13 +272,15 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
*proc_id = 0x14000217;
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu;
qemu_irq *irqp;
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
@ -438,7 +438,7 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
vexpress_binfo.smp_loader_start = map[VE_SRAM];
vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
arm_load_kernel(first_cpu, &vexpress_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo);
}
static void vexpress_a9_init(ram_addr_t ram_size,

4
hw/xen_machine_pv.c
View File

@ -36,6 +36,7 @@ static void xen_init_pv(ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
X86CPU *cpu;
CPUX86State *env;
DriveInfo *dinfo;
int i;
@ -48,7 +49,8 @@ static void xen_init_pv(ram_addr_t ram_size,
cpu_model = "qemu32";
#endif
}
env = cpu_init(cpu_model);
cpu = cpu_x86_init(cpu_model);
env = &cpu->env;
env->halted = 1;
/* Initialize backend core & drivers */

10
hw/xilinx_zynq.c
View File

@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env = NULL;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
@ -66,12 +66,12 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
cpu_model = "cortex-a9";
}
env = cpu_init(cpu_model);
if (!env) {
cpu = cpu_arm_init(cpu_model);
if (!cpu) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
irqp = arm_pic_init_cpu(env);
irqp = arm_pic_init_cpu(cpu);
cpu_irq = irqp[ARM_PIC_CPU_IRQ];
/* max 2GB ram */
@ -137,7 +137,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
zynq_binfo.nb_cpus = 1;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;
arm_load_kernel(first_cpu, &zynq_binfo);
arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
}
static QEMUMachine zynq_machine = {

26
hw/z2.c
View File

@ -301,7 +301,7 @@ static void z2_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
uint32_t sector_len = 0x10000;
PXA2xxState *cpu;
PXA2xxState *mpu;
DriveInfo *dinfo;
int be;
void *z2_lcd;
@ -313,7 +313,7 @@ static void z2_init(ram_addr_t ram_size,
}
/* Setup CPU & memory */
cpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);
mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
@ -337,25 +337,25 @@ static void z2_init(ram_addr_t ram_size,
}
/* setup keypad */
pxa27x_register_keypad(cpu->kp, map, 0x100);
pxa27x_register_keypad(mpu->kp, map, 0x100);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc,
pxa2xx_mmci_handlers(mpu->mmc,
NULL,
qdev_get_gpio_in(cpu->gpio, Z2_GPIO_SD_DETECT));
qdev_get_gpio_in(mpu->gpio, Z2_GPIO_SD_DETECT));
type_register_static(&zipit_lcd_info);
type_register_static(&aer915_info);
z2_lcd = ssi_create_slave(cpu->ssp[1], "zipit-lcd");
bus = pxa2xx_i2c_bus(cpu->i2c[0]);
z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
bus = pxa2xx_i2c_bus(mpu->i2c[0]);
i2c_create_slave(bus, "aer915", 0x55);
wm = i2c_create_slave(bus, "wm8750", 0x1b);
cpu->i2s->opaque = wm;
cpu->i2s->codec_out = wm8750_dac_dat;
cpu->i2s->codec_in = wm8750_adc_dat;
wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
mpu->i2s->opaque = wm;
mpu->i2s->codec_out = wm8750_dac_dat;
mpu->i2s->codec_in = wm8750_adc_dat;
wm8750_data_req_set(wm, mpu->i2s->data_req, mpu->i2s);
qdev_connect_gpio_out(cpu->gpio, Z2_GPIO_LCD_CS,
qdev_connect_gpio_out(mpu->gpio, Z2_GPIO_LCD_CS,
qemu_allocate_irqs(z2_lcd_cs, z2_lcd, 1)[0]);
if (kernel_filename) {
@ -363,7 +363,7 @@ static void z2_init(ram_addr_t ram_size,
z2_binfo.kernel_cmdline = kernel_cmdline;
z2_binfo.initrd_filename = initrd_filename;
z2_binfo.board_id = 0x6dd;
arm_load_kernel(&cpu->cpu->env, &z2_binfo);
arm_load_kernel(mpu->cpu, &z2_binfo);
}
}

2
target-s390x/cpu.c
View File

@ -20,7 +20,7 @@
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "cpu-qom.h"
#include "cpu.h"
#include "qemu-common.h"
#include "qemu-timer.h"

10
target-s390x/cpu.h
View File

@ -105,6 +105,8 @@ typedef struct CPUS390XState {
QEMUTimer *cpu_timer;
} CPUS390XState;
#include "cpu-qom.h"
#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
{
@ -271,7 +273,7 @@ static inline int get_ilc(uint8_t opc)
#define ILC_LATER_INC_2 0x22
CPUS390XState *cpu_s390x_init(const char *cpu_model);
S390CPU *cpu_s390x_init(const char *cpu_model);
void s390x_translate_init(void);
int cpu_s390x_exec(CPUS390XState *s);
void cpu_s390x_close(CPUS390XState *s);
@ -314,7 +316,7 @@ static inline void kvm_s390_interrupt_internal(CPUS390XState *env, int type,
{
}
#endif
CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr);
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
void s390_add_running_cpu(CPUS390XState *env);
unsigned s390_del_running_cpu(CPUS390XState *env);
@ -340,7 +342,7 @@ static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
env->aregs[1] = newtls & 0xffffffffULL;
}
#define cpu_init cpu_s390x_init
#define cpu_init(model) (&cpu_s390x_init(model)->env)
#define cpu_exec cpu_s390x_exec
#define cpu_gen_code cpu_s390x_gen_code
#define cpu_signal_handler cpu_s390x_signal_handler
@ -994,6 +996,4 @@ static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
env->psw.addr = tb->pc;
}
#include "cpu-qom.h"
#endif

4
target-s390x/helper.c
View File

@ -70,7 +70,7 @@ void s390x_cpu_timer(void *opaque)
}
#endif
CPUS390XState *cpu_s390x_init(const char *cpu_model)
S390CPU *cpu_s390x_init(const char *cpu_model)
{
S390CPU *cpu;
CPUS390XState *env;
@ -86,7 +86,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
env->cpu_model_str = cpu_model;
qemu_init_vcpu(env);
return env;
return cpu;
}
#if defined(CONFIG_USER_ONLY)

12
target-s390x/kvm.c
View File

@ -292,8 +292,10 @@ static int handle_diag(CPUS390XState *env, struct kvm_run *run, int ipb_code)
return r;
}
static int s390_cpu_restart(CPUS390XState *env)
static int s390_cpu_restart(S390CPU *cpu)
{
CPUS390XState *env = &cpu->env;
kvm_s390_interrupt(env, KVM_S390_RESTART, 0);
s390_add_running_cpu(env);
qemu_cpu_kick(env);
@ -333,6 +335,7 @@ static int handle_sigp(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
uint16_t cpu_addr;
uint8_t t;
int r = -1;
S390CPU *target_cpu;
CPUS390XState *target_env;
cpu_synchronize_state(env);
@ -353,14 +356,15 @@ static int handle_sigp(CPUS390XState *env, struct kvm_run *run, uint8_t ipa1)
parameter = env->regs[t] & 0x7ffffe00;
cpu_addr = env->regs[ipa1 & 0x0f];
target_env = s390_cpu_addr2state(cpu_addr);
if (!target_env) {
target_cpu = s390_cpu_addr2state(cpu_addr);
if (target_cpu == NULL) {
goto out;
}
target_env = &target_cpu->env;
switch (order_code) {
case SIGP_RESTART:
r = s390_cpu_restart(target_env);
r = s390_cpu_restart(target_cpu);
break;
case SIGP_STORE_STATUS_ADDR:
r = s390_store_status(target_env, parameter);