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tcg/mips: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
10e1fd2784
commit
e3a650cd9d
@ -78,13 +78,11 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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#define TCG_TMP2 TCG_REG_T8
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#define TCG_TMP3 TCG_REG_T7
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG TCG_REG_S7
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#endif
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_REG_TB TCG_REG_S6
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#else
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#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO)
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#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; })
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#endif
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/* check if we really need so many registers :P */
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@ -1279,130 +1277,129 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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a_bits = h->aa.align;
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a_mask = (1 << a_bits) - 1;
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#ifdef CONFIG_SOFTMMU
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unsigned s_mask = (1 << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int add_off = offsetof(CPUTLBEntry, addend);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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if (tcg_use_softmmu) {
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unsigned s_mask = (1 << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int add_off = offsetof(CPUTLBEntry, addend);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
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/* Extract the TLB index from the address into TMP3. */
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if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
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tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_dsrl(s, TCG_TMP3, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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}
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
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/* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
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if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
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/* Load the (low half) tlb comparator. */
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tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
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cmp_off + HOST_BIG_ENDIAN * 4);
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} else {
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tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
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}
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if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
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}
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/*
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* Mask the page bits, keeping the alignment bits to compare against.
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* For unaligned accesses, compare against the end of the access to
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* verify that it does not cross a page boundary.
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*/
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tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
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if (a_mask < s_mask) {
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if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
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tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
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} else {
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tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_mask);
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}
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
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} else {
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
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}
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/* Zero extend a 32-bit guest address for a 64-bit host. */
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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tcg_out_ext32u(s, TCG_TMP2, addrlo);
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addrlo = TCG_TMP2;
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}
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
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/* Load and test the high half tlb comparator. */
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if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
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/* delay slot */
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
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ldst->label_ptr[1] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
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}
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/* delay slot */
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base = TCG_TMP3;
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
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#else
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if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
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/* Extract the TLB index from the address into TMP3. */
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if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
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tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_dsrl(s, TCG_TMP3, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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}
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
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/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
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if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
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/* Load the (low half) tlb comparator. */
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tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
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cmp_off + HOST_BIG_ENDIAN * 4);
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} else {
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tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
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}
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if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
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}
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/*
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* Mask the page bits, keeping the alignment bits to compare against.
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* For unaligned accesses, compare against the end of the access to
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* verify that it does not cross a page boundary.
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*/
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tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
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if (a_mask < s_mask) {
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tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
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|| addr_type == TCG_TYPE_I32
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? OPC_ADDIU : OPC_DADDIU),
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TCG_TMP2, addrlo, s_mask - a_mask);
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
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} else {
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
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}
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/* Zero extend a 32-bit guest address for a 64-bit host. */
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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tcg_out_ext32u(s, TCG_TMP2, addrlo);
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addrlo = TCG_TMP2;
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}
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ldst->label_ptr[0] = s->code_ptr;
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if (use_mips32r6_instructions) {
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tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
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} else {
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tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
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tcg_out_nop(s);
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}
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}
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tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
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base = addrlo;
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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tcg_out_ext32u(s, TCG_REG_A0, base);
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base = TCG_REG_A0;
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}
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if (guest_base) {
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if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
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} else {
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
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TCG_GUEST_BASE_REG);
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/* Load and test the high half tlb comparator. */
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if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
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/* delay slot */
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
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ldst->label_ptr[1] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
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}
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/* delay slot */
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base = TCG_TMP3;
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
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} else {
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if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
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ldst->label_ptr[0] = s->code_ptr;
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if (use_mips32r6_instructions) {
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tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
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} else {
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tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
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tcg_out_nop(s);
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}
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}
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base = addrlo;
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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tcg_out_ext32u(s, TCG_REG_A0, base);
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base = TCG_REG_A0;
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}
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if (guest_base) {
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if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
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} else {
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
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TCG_GUEST_BASE_REG);
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}
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base = TCG_REG_A0;
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}
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base = TCG_REG_A0;
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}
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#endif
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h->base = base;
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return ldst;
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@ -2465,8 +2462,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
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}
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#ifndef CONFIG_SOFTMMU
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if (guest_base != (int16_t)guest_base) {
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if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) {
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/*
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* The function call abi for n32 and n64 will have loaded $25 (t9)
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* with the address of the prologue, so we can use that instead
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@ -2479,7 +2475,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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}
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#endif
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
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