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vmstate: port ppce500_pci

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Signed-off-by: Juan Quintela <quintela@redhat.com>
This commit is contained in:
Juan Quintela 2010-12-02 15:29:42 +01:00 committed by Anthony Liguori
parent f0ab24ce69
commit e0433ecc6e
1 changed files with 40 additions and 47 deletions
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87
hw/ppce500_pci.c
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@ -216,56 +216,49 @@ static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
static void ppce500_pci_save(QEMUFile *f, void *opaque)
{
PPCE500PCIState *controller = opaque;
int i;
pci_device_save(controller->pci_dev, f);
for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
qemu_put_be32s(f, &controller->pob[i].potar);
qemu_put_be32s(f, &controller->pob[i].potear);
qemu_put_be32s(f, &controller->pob[i].powbar);
qemu_put_be32s(f, &controller->pob[i].powar);
static const VMStateDescription vmstate_pci_outbound = {
.name = "pci_outbound",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT32(potar, struct pci_outbound),
VMSTATE_UINT32(potear, struct pci_outbound),
VMSTATE_UINT32(powbar, struct pci_outbound),
VMSTATE_UINT32(powar, struct pci_outbound),
VMSTATE_END_OF_LIST()
}
};
for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
qemu_put_be32s(f, &controller->pib[i].pitar);
qemu_put_be32s(f, &controller->pib[i].piwbar);
qemu_put_be32s(f, &controller->pib[i].piwbear);
qemu_put_be32s(f, &controller->pib[i].piwar);
static const VMStateDescription vmstate_pci_inbound = {
.name = "pci_inbound",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT32(pitar, struct pci_inbound),
VMSTATE_UINT32(piwbar, struct pci_inbound),
VMSTATE_UINT32(piwbear, struct pci_inbound),
VMSTATE_UINT32(piwar, struct pci_inbound),
VMSTATE_END_OF_LIST()
}
qemu_put_be32s(f, &controller->gasket_time);
}
};
static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
{
PPCE500PCIState *controller = opaque;
int i;
if (version_id != 1)
return -EINVAL;
pci_device_load(controller->pci_dev, f);
for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
qemu_get_be32s(f, &controller->pob[i].potar);
qemu_get_be32s(f, &controller->pob[i].potear);
qemu_get_be32s(f, &controller->pob[i].powbar);
qemu_get_be32s(f, &controller->pob[i].powar);
static const VMStateDescription vmstate_ppce500_pci = {
.name = "ppce500_pci",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
vmstate_pci_outbound, struct pci_outbound),
VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
vmstate_pci_outbound, struct pci_inbound),
VMSTATE_UINT32(gasket_time, PPCE500PCIState),
VMSTATE_END_OF_LIST()
}
for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
qemu_get_be32s(f, &controller->pib[i].pitar);
qemu_get_be32s(f, &controller->pib[i].piwbar);
qemu_get_be32s(f, &controller->pib[i].piwbear);
qemu_get_be32s(f, &controller->pib[i].piwar);
}
qemu_get_be32s(f, &controller->gasket_time);
return 0;
}
};
PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
@ -314,8 +307,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
PCIE500_REG_SIZE, index);
/* XXX load/save code not tested. */
register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
1, ppce500_pci_save, ppce500_pci_load, controller);
vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
controller);
return controller->pci_state.bus;